logical architecture 中文意思是什麼
logical architecture
解釋
邏輯架構- logical : adj. 1. 邏輯的，邏輯上的；邏輯學上的。2. 合乎邏輯的。3. 邏輯上必然的。adv. -ly ,-ness n.
- architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
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The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data
具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。 -
Finding a feasible and efficient load balanced strategy for the ultra - scalable multi - plane multi - stage switch architecture is a top of nowadays research. the dissertation proposes a two - stage load balanced scheme for the ultra - scalable multi - plane multi - stage switch architecture based self - routing and non - blocking permutation benes network. the approach uses reasonable and efficient logical queueing strategy and schedule scheme in ingress traffic managers and switch planes to realize the two - stage load balancing of ip traffic which for different destination addresses
本文提出一種適用於基於完全可重排無阻塞benes拓撲構建的多平面多路徑（多級）超大容量交換結構的兩級負載均衡策略，通過在輸入流量管理器和benes交換平面內部實施合理而高效的隊列組織調度方法，有效實現了基於不同目的地址的ip流量在兩個層次上的負載均衡，較好彌補了ciscocrs - 1系統在平面選擇和中間級選擇時所採用的簡單隨機或輪循方案的不足。 -
This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed
本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。 -
Based on the fundamental study, a kind of rational cims architecture of the hydro - junction is given out, including its rational function structure, logical structure, and hierarchical control, decision - scheduling - field ' s control application system structure
在此基礎上，提出了水利樞紐cims的合理體系結構，即給出了合理的功能結構、邏輯結構、遞階控制結構、決策-調度-現場控制應用系統結構。 -
A logical view of the web services architecture is shown in
展示了web服務體系結構的一個邏輯視圖。 -
Investigation and analyzing has been made by the science and the industry for architecture of the network processor and network applications to testify the high benefits that could be brought by good combination of the logic of network application and the parallel infrastructure of the network processor, which confirms that the logical parallelization in network applications and the paralleled hardware structure of network processor are the promising basics for potential excavating of network hardware and developing of high quality network applications
學術界和工業界致力於對網路處理器架構和網路應用程序二者各自的特性進行研究和分析，用以說明網路應用程序本身的邏輯特性和網路處理器的并行架構相得益彰。通過研究可以看出，網路應用程序本身的多個特性使其具有天然的可并行邏輯，這為充分挖掘其并行性和開發基於網路處理器的高質量高性能的應用程序奠定了基礎。再者，網路處理器專有的硬體架構為應用程序的并行執行提供了硬體基礎。 -
Based on the discussion of the two main platforms on which distributed enterprise applications can be built, j2ee was selected as the infrastrcture of our inspection platform. the inspection platform was designed from the usecase view, logical view and deployment view respectively. model - view - controler ( mvc ) design pattern was used in the softeware architecture design
Net平臺的比較分析，選擇將系統監測中心構建在j2ee規范之上，然後利用uml建模技術分別從用例視圖、邏輯視圖、部署視圖三個角度闡述了系統監測平臺的總體設計，整個軟體的結構基於mvc （視圖、數據和控制分離）的設計模式。 -
Abstract : because of its concise and skilled logical language, ticino school becomes the model combining basic principles of modern architecture with local culture
文摘:瑞士的提契諾學派以他們精練而嫻熟的邏輯語言成為現代建築的基本原理與地方文化結合的典範。 -
As the development of the information technology, the sub - system of the healthcare realizes its information systems in different levels. in order to resolve the problem about the data exchanging among all of heterogeneous systems, there must be architecture to support the integration among these heterogeneous systems, so as to realize the close relation, mutual restriction and data share among all the system by logical information stream
隨著信息技術的高度發展，在醫療機構內部的從屬部門在不同程度上實現了自己的信息系統;針對這些異構的信息系統進行數據交換的問題，必須有一種合理的構架體系支持這些異構系統間的集成，使各個異構系統之間以合理的信息流實現緊密聯系、相互制約、數據共享。 -
The model usam consists of parts, connectors, interfaces and constraints, described with use case view, logical view, component view and deployment view. it also discussed the usam - based software development process and the architecture - centered, object - orient, component - based development strategy
該模型由組件、連接件、介面件和約束組成，採用uml的一個子集作為體系結構建模語言，用例視圖、邏輯視圖、構件視圖和配置視圖表示模型的4個視圖。 -
In the first part of this paper, different kinds of usual network architecture of parallel - processing multi - processors are studied. based on adsp - 21160 serial digital signal processors from ad company, close - coupled flexible hardware network architecture is selected as the network architecture of the system, because of which the hardware logical architecture of the system can be recomposed on line according to the acquirement of different algorithms
本文第一部分研究了各種常見的并行處理網路結構，基於ad公司的adsp - 21160系列數字信號處理晶元，選擇緊耦合的柔性硬體結構作為該系統的并行處理結構，使得系統的硬體邏輯結構可以根據演算法的要求在線重組。 -
A shared - nothing architecture allows a workload to be divided into multiple logical units or partitions, and each logical unit is allocated with its own computing resources, such as processors, memory, and disks
無共享的體系結構允許將工作負載分為多個邏輯單元或分區，並給每個邏輯單元分配它自己的計算資源，如處理器、內存和磁盤。 -
Based on the theory model of quantum computing and the quantum computing technique in existence, we have proposed the cooperating architecture of quantum computer. in this architecture, it uses the classic processor as its control unit, and use the quantum arithmetic logical unit and quantum memory unit as its co - process unit
針對這種情況，通過對量子計算技術的深入研究，全面剖析現有量子計算系統，借鑒經典計算機中的研究成果，作者提出了協同量子計算機體系結構方案，在該方案中，使用經典計算機完成量子程序中的常規數據處理和程序邏輯控制，而將量子計算部件做為協處理器，只負責完成量子計算。 -
But by analyzing the data warehouse architecture, it can be found that the load imbalance of computational logical result in overload for the integrator, not enough positivity for information sources, and high price for view maintenance
但是分析他們的體系結構發現，計算邏輯負載的不平衡造成集成器負擔過重，信息源的主動性不強，系統的維護開銷大等缺點。 -
It minimizes the degree of coupling between the objects involved in maintaining and presenting data, and divides functionality among its logical and non - logical part. moreover, the mvc architecture is straightforward to map these concepts into the domain of multitier web - based enterprise applications
它降低了處理和顯示數據的對象間的偶合性，將邏輯與非邏輯功能部分隔離開，並且這一概念在基於web方式的多層應用程序領域中得以廣泛應用。 -
The oma framework is a logical architecture that does not propose any specific topology or physical location of servers
Oma框架是一個邏輯架構，它並沒有建議任何特定的拓補或服務器的物理位置。 -
After analyzing the urban traffic control system ' s development tendency of integration and intelligentization, this paper researched on the basic principle, prototype system and the system architecture of the new iutcs, and analyzed the physical architecture and logical architecture which consist of three layers : central network control layer, area network control layer and intersection control layer
介紹了目前城市交通控制系統的發展趨勢集成化和智能化，在此基礎上研究了所開發的集成化城市交通控制系統的開發原理、系統原型和系統結構（包括系統物理結構及邏輯結構） 。 -
Describes the logical architecture of the transaction log
介紹事務日誌的邏輯體系結構。 -
Transaction log logical architecture
事務日誌邏輯體系結構 -
The logical architecture, protocol, the encoder algorithm, the decoder algorithm and the electronics specification of the tmds which is the core of the dvi and means transition minimized differential signal are described in particular in this paper. and the synchronization and data recovering which mean the central problem in the high speed serial data communications are also analyzed
本文以dvi介面通訊協議為主線，詳細介紹和分析了作為介面核心內容的tmds ? ?最小變化差分信號的邏輯架構、通訊協議的編碼演算法、解碼演算法、 tmds信號的電氣規范等問題，並著重分析了作為高速串列通訊的關鍵問題的鏈路時鐘同步與數據恢復問題。
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