processor architecture 中文意思是什麼

processor architecture 解釋
處理機體系結構
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. Based on cae system for construction curtain wall structure analysis, it presented a kind of parametric design language w - spdl and the architecture of its processor especially for construction curtain wall structure analysis, which can greatly enhance compound features of the system. it is also helpful to further developing for the system, batch commands processing, parametric design of structure analysis and simplifying the operation flows

    基於建築幕墻結構計算機輔助工程分析系統，建立了一套適合建築幕墻結構分析的參數化設計語言w - spdl ，並提出了一種開放性w - spdl宏處理器體系結構，提高了系統綜合性能，並為基於系統進行二次開發、批命令處理、結構分析參數化設計以及簡化用戶操作流程等提供了支持。
  2. Tms320vc5402 is a fixed - point digital signal processor, made by texas instruments incorporated, which is 16 - bit word length. vc5402 has enhanced harvard architecture built around one program bus, three data buses, and four address buses for increased performance and versatility

    另外，採用mcs - 51系列cpu作為採集處理卡板載mcu也存在一些比較嚴重的問題，如cpu的指令執行速度慢，總線帶寬窄等缺點，不能完成數據的高速處理。
  3. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  4. Each assembly is specified in the manifest by its name, version number and processor architecture

    清單中的每個程序集都是按照程序集的名稱、版本號和處理器結構指定的。
  5. Even if an expression is deterministic, if it contains float expressions, the exact result may depend on the processor architecture or version of microcode

    即使是確定性表達式，如果其中包含浮點表達式，則準確結果也會取決于處理器體系結構或微代碼的版本。
  6. Secondly, the scheme of the management machine of power communication, whose hardware architecture is based on c32 digital signal processor ( dsp ) and software is based on real time operation system ( rtos ), is discussed. and also the possibility of realization of the scheme is demonstrated

    然後，給出了電力自動化通信管理機的設計方案，介紹了論文所採用的硬體基於c32數字信號處理器（ dsp ）和軟體以實時操作系統（ rots ）為平臺的方案，並論證其可行性。
  7. Video encoder computation efficiency optimization based on trimedia processor architecture feather

    處理器體系結構的視頻編碼效率優化
  8. Gets or sets the processor architecture of the assembly

    獲取或設置程序集的處理器結構。
  9. Investigation and analyzing has been made by the science and the industry for architecture of the network processor and network applications to testify the high benefits that could be brought by good combination of the logic of network application and the parallel infrastructure of the network processor, which confirms that the logical parallelization in network applications and the paralleled hardware structure of network processor are the promising basics for potential excavating of network hardware and developing of high quality network applications

    學術界和工業界致力於對網路處理器架構和網路應用程序二者各自的特性進行研究和分析，用以說明網路應用程序本身的邏輯特性和網路處理器的并行架構相得益彰。通過研究可以看出，網路應用程序本身的多個特性使其具有天然的可并行邏輯，這為充分挖掘其并行性和開發基於網路處理器的高質量高性能的應用程序奠定了基礎。再者，網路處理器專有的硬體架構為應用程序的并行執行提供了硬體基礎。
  10. Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels. this paper present the architecture model of smpdca, and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi - ported cache

    Smpdca結構具有六個突出優勢：相對于大規模的超標量結構而言， smpdca結構的控制邏輯復雜性明顯要低得多；相對于通過共享主存來實現處理器之間的通信的結構而言，通過一個共享的第一級數據cache來實現處理器之間的通信的smpdca結構能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護開銷；數據cache命中率提高；便於smp （對稱多處理器結構）的軟體重用；從多個層次上開發程序的并行性。
  11. A processor architecture is disclosed including a fetcher, packet unit and branch target buffer

    母案摘要:揭露一種包含指令取器、封裝單元及分支目標緩沖器的處理器架構。
  12. Query processor architecture

    查詢處理器體系結構
  13. Then, the work researches multithread processor architecture based on the armp. this dissertation focused on the branch predictor of high performance processor and fetch unit of selective execution of multithread architecture

    接著，本文以armp為基礎深入了解國內外目前最先進的多線程處理器系統結構研究工作，明確了該領域研究的發展方向和研究難點。
  14. You also need to know whether the jvm correctly determines host processor architecture so that the jit compiler can produce the correct set of instructions for that architecture

    您還需要知道jvm能否確定主機處理器的體系結構，以使得jit編譯器可以為那個體系結構生成正確的指令集。
  15. The processor architecture of the application

    應用程序的處理器體系結構。
  16. The preferred target processor architecture

    首選的目標處理器結構。
  17. Gets the target processor architecture for the application

    獲取應用程序的目標處理器體系結構。
  18. Contains values that represent the registers associated with a given processor architecture

    包含表示與指定處理器結構關聯的寄存器的值。
  19. First, this page introduce the development of embedded system and the general principle of embedded system. arm architecture is the mainstream among all sorts of processor architecture, a relatively particular study has been done about the lpc2290 microcontroller that is based on arm 7 core

    然後研究了32位嵌入式系統應用中佔主流地位的arm處理器的體系結構，包括arm微處理器體系結構、 arm體系結構對操作系統的支持、基於arm核的晶元選擇等，並從應用的角度分析了arm7核的lpc2290微控制器。
  20. And described three ways in detail separately : more access ports and non - blocking cache and quick hit buffer ( qhb ), and analyzed their performance. smpdca is a promising processor architecture

    並分別對更多的訪問埠、非阻塞cache以及快速命中緩沖區（ qhb ）等三種方法進行了詳細描述和性能模擬分析。
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