switched modulator 中文意思是什麼
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The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox
本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。 -
And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown
調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。 -
After analysing the stability of high - order single - loop modulator, a stable third - order single - loop modulator has been implemented. this novel architecture is more insensitive to the performance of analog circuit and the matching of component. the experimental modulator has been designed with fully differential switched - capacitor circuit
在分析高階單環路調制器穩定性的基礎上，成功設計了一位量化三階單環路-調制器結構，該結構對電路參數不敏感，進一步降低了后續模擬電路設計的性能指標要求。
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