synthesis high-level 中文意思是什麼

synthesis high-level 解釋
高階合成
  • synthesis : n. （pl. -ses ） 綜合，【化學】合成；【邏輯學】綜合（法）；【語言學】綜合（性）；語詞的合成；【醫學】接合；【物理學】合成綜合。
  • high : adj 1 高的〈指物，形容人的身高用 tall〉；高處的；高地的。2 高級的，高等的，高位的，重要的。3 高尚...
  • level : n 1 水平儀，水準儀；水準測量。2 水平線，水平面；水平狀態；平面，平地。3 水平，水準；水位；標準；...
  1. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  2. 3 ) the paper discussed the theory and the method of asic high - level synthesis : ? nalyzed the synthesizable problems of vhdl language systematically, and discussed the establishment and the implementation methods of vhdl synthesis subclasses

    3 ）本文對asic高級綜合的理論與方法進行了深入的探討：系統地分析了vhdl語言的可綜合性問題，並探討了vhdl綜合子集的確立及實現方法。
  3. In this paper we put forward two kinds of high level synthesis method based on researching the technology adopted in other hls or hls optimization. one is a specific hls for control intensive designs, we adopt control - flow graph as the internal representation and use the speculation technology during the scheduling

    本文提出了兩種類型的高級綜合方法，其一是提出了針對控制佔主要部分的電路的高級綜合方法，該方法採用了基於控制流圖的中間表示結構，在調度過程中採用了針對該電路特點的推測技術。
  4. ( 3 ) the paper researched two powerfully practical kinds of attempering method of high - level synthesis, which were based on function cell maximal utility rate and conditional structure

    本文深入研究了實用性強的高級綜合的兩種調度演算法，即基於功能單元最大利用率的調度演算法和條件結構的調度演算法。
  5. High level synthesis tool can choose best scheme in a large design space

    高級綜合工具可以在很大的設計空間中選擇最優的設計方案。
  6. Lastly, we use the high level synthesis tool synplify to test the validity of the improving mcu. according to the synthesis result, the system clock reached about 66mhz

    最後，採用synplicity公司的高層綜合工具synplify對所設計的mcu進行了綜合，綜合結果驗證了改進型mcu滿足了要求，工作頻率達到66mhz 。
  7. Synthesis and optimization of loop in high - level synthesis

    高級綜合中循環的綜合方法研究
  8. Language requirements for high - level synthesis

    高級綜合的語言要求
  9. Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping. explicit redundancy can not improve the performance, but increases power consumption, enlarges circuit area and decreases its testability, so it should be removed. this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability

    文摘:高級綜合結果中常量元件和輸出懸空埠導致門級工藝映射結果中存在顯式冗餘.顯式冗餘無助於提高電路性能，反而增加功耗，降低電路的可測試性，使電路面積增大，應予消除.文中提出了顯式冗餘的隊列循環優化演算法，完全消除了此類冗餘，從而有效地減少了生成電路的基片面積，提高了電路的可測試性
  10. First, the basic raster graphics algorithms for drawing 2d primitives are introduced, including edge coherence and the scan - line algorithm of triangle, brush algorithm of thick line ( and its improved method ) and midpoint circle and ellipse algorithm ; and the current situation of the advanced algorithms is also involved. second, the mapping of high level programming language to hardware description language is described, some principles of the conversion of algorithm to state machine are proposed also ; then, the implementation of basic graphics in hardware is discussed in detail, the state machines are drawn in the paper, and the interfaces of hardware are defined, block diagrams too, and the advanced algorithm of conic is proved ; finally, some issues about test are described, the results of simulation and synthesis are given in the last, and some detailed data are displayed in the appendix

    首先介紹了現有的基本圖形生成演算法，包括三角形邊相關掃描演算法，寬直線的線刷子演算法及其改進和圓形、橢圓的生成演算法，同時介紹了加速演算法的研究現狀；然後，討論了高級語言描述到硬體描述語言的映射，提出了演算法到狀態機抽象的規律；接著具體討論了基本圖形的硬體實現，給出了各演算法的狀態機圖，介面定義和實現框架，並且從理論角度給出了二次曲線加速演算法的證明：最後採用軟體工具進行測試驗證，給出了模擬、綜合實現的結果，並在附錄中有詳細的實驗結果數據。
  11. High - level synthesis has been developed on the base of logic synthesis. it starts from the behavioral design description of high - level and outputs the structural description with lower level as a result. so the design complexity can be simplified and design efficiency can be raised

    高級綜合是在邏輯綜合的基礎上發展而來的，它從高層次的行為描述開始，自動綜合出低層次的結構描述，從而降低了設計復雜度，提高了設計效率。
  12. This paper focuses on the basic concept of the - converters, designs and implements decimation filter. we use the advanced hld ( high - level design ) technique to describe combfilter. finally, this paper presents the process of synthesis and implementation

    在該課題的研究中，採用了目前asic設計中最先進的高層次設計方法，使用硬體描述語言verilog對其進行描述，最後完成了系統模擬和綜合。
  13. Study on synthesis of citrate by citric acid high - level fatty alcohol and properities of emulsifying

    高級脂肪醇合成檸檬酸酯及其乳化性能的研究
  14. High - level synthesis of timing and synchronization in i o communication

    通訊中時序和同步的高級綜合
  15. This paper researched the asic design in the automation system of a kind of auv with high - level design method based on vhdl high - level synthesis

    本文採用基於vhdl高級綜合的高層次設計方法對某型水下航行器自控系統的集成設計進行了研究。
  16. 4 ) the paper discussed high synthesis realization in the automatic system of the auv with < < talent 2000 asic high - level automatic design system > >

    4 ）本文藉助于《 talent2000asic高層次自動設計系統》對某型水下航行器自控系統的高級綜合實現進行了初步探討。
  17. ? he paper established a midst data format figured by high - level synthesis design, which is cdfg model, put forward the cdfg denotation of basic sentences in vhdl synthesis subclasses chose in the paper and gave out the automatic creation methods of cdfg

    本文建立了一個高級綜合設計表示的中間數據格式，即cdfg模型，提出了本文所選定的vhdl綜合子集中基本語句的cdfg表示，給出了cdfg的自動生成方法。
  18. In the traditional design flow, synthesis is the typical mapping process, it is the process that high level resultant seeking suitable library component in the lower level library

    在傳統設計流程中，綜合是典型的映射過程，是高層次的生成物在低一個層次的庫中尋找合適的庫元件的過程。
  19. All the modules of risc mcu core were described with verilog hdl and synthesized with high - level synthesis eda tools. then the risc mcu was implemented in fpga device

    所有模塊都採用verilog硬體描述語言進行設計描述，使用eda工具進行功能模擬、綜合，並在fpga器件上完成了系統的硬體驗證。
  20. Chemical synthesis of human interleukin - 18 gene and its high - level expression in e. coli

    人白細胞介素18基因化學合成及其在大腸桿菌中高表達
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