top-down simulation 中文意思是什麼

top-down simulation 解釋
自頂向下模擬
  • top : n （opp bottom foot）1 頂，頂部，頂端。2 頭，頭頂；尖端；樹梢，樹頂；（事物的）上層部分。3 最高位...
  • down : adv （downmost）1 向下（面）；下，降；在下（面）。 come down 下來；下（樓）來；（雨等）落下。 The...
  • simulation : n. 假裝；模擬；裝病，裝瘋；【生物學】擬態，擬色。
  1. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  2. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  3. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  4. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  5. Procedures for developing solid cost, schedule, and resource estimates. conceptual, preliminary, and definitive estimates. top - down vs. bottom - up estimates. parametric estimates. life - cycle estimating. use of monte carlo simulation

    對成本、進程、資源進行評估的程序。概念的、初始的和結論性評估。自上而下的與自下而上的評估。參數評估。生命周期評估。蒙特卡羅模擬法的使用。
  6. Based on the cfd simulation, analyses and compares four air distribution modes using relevant evaluating indexes, and concludes that the top - supplying and opposite down - exhausting air distribution is an optimal mode for isolation wards

    摘要採用cfd數值模擬的方法，利用相關評價指標對四種不同氣流分佈方式進行了比較分析，認為天花板頂送異側下排是較為理想的氣流分佈方式。
  7. In addition, it adopts dis ( distributed interactive simulation ) and the " top - down work downward " constructive design method to prooftest, modify and perfect the process and date flow, including the integrality, rationality, practicality and reliability of the system

    從工作、數據流程及系統的完整性、合理性、使用性和可靠性等方面進行檢驗、修改、完善，建立了較為實用合理的數據庫系統，滿足了模擬任務要求。
  8. The design of mcs - 51 microcontroller is followed the top - down design way, including system partition coding ( vhdl ) rtl simulation synthesis, gate level simulation ect

    對mcs ? 51單片機進行正向設計，包括系統劃分、編寫代碼、 rtl級模擬與綜合、門級模擬等。
  9. By the top - down way, the design was divided into several modules according to their functions, which were characterized respectively. meanwhile, behavior description, rtl function simulation and logic synthesis were carried out

    在充分了解驅動電路系統的基礎上，採用「自上向下」的設計方法將其劃分為幾個功能模塊，並對它們分別進行了行為描述、 rtl功能模擬、邏輯綜合。
  10. In the fec part, rs ( reed - solomon ) code and interleave are chosen as the basic elements of the error correction system at first ; then the coding parameter and data structure are determined based on the results of matlab simulation ; at last, hdl modules are implemented in fpga using verilog hdl, test results and simulation diagrams are presented as well. in the designing process, the proper division of the modules and the cooperation between modules need a lot of consideration, and the top - down method is adopted to solve these questions

    在前向糾錯的設計部分，文章首先根據系統的誤比特率要求選擇了rs （ reed - solomon ）碼和交織器作為前向糾錯部分的基本構架，再根據matlab的模擬結果得到了具體的編解碼參數和碼字結構，最後在fpga中用硬體描述語言veriloghdl實現了各個編解碼模塊，並給出了測試數據、實現結果及時序模擬波形圖。
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