互連延時 的英文怎麼說
中文拼音 [hùliányánshí]
互連延時
英文
interconnection time delay-
The scheme takes advantages of repeaters and low - swing differential - signaling circuits on driving long wires in different length, and optimally inserts them along the wire in order to decrease delay and power of interconnects
該方法利用中繼驅動器和低擺幅差分信號電路在驅動不同長度連線時的優點，將它們混合插入到連線的合適位置，從而降低互連的延時和功耗。As the technology advances into deep sub - micron era, crosstalk reduction is of paramount importance for signal integrity. simultaneous shield insertion and net ordering sino has been shown to be effective to reduce both capacitive and inductive couplings
隨著集成電路工藝發展到深亞微米技術，互連線串擾問題變得相當重要，它與互連線時延問題成為了決定電路性能的主要因素。In a word, this paper has made a common and deep analysis of interconnect delay and a whole depiction of improvement methods for interconnect delay
總之，本文對ulsi銅互連延時進行了普遍和深入的分析，對改善延時的方法也進行了全面的闡述。When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。Interconnection generates in 1994, when china union was founded. with the development of telecommunication industry, interconnection presents different states, at the beginning, it ’ s the problem of weak & delay signal because of the telegraphic network ’ s low quality, then it becomes the situation of connected but influent, by 2003, it badly deteriorated while both sides destroyed the cable, interdicted communications by people, so people focus on interconnection
互聯互通問題早期表現為因電信網本身質量問題而導致的網間信號不好、簡訊延時等;接著，發展為固網、移動網之間，本地網、 ip長途網之間不時出現的不通、不暢等問題;而在2002年、 2003年問題已經嚴重到互相砍斷傳輸電纜、人為阻斷網間通信等惡性事件接連發生。Abstract : an algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented. given a two - terminal net, the algorithm can minimize the total number of buffers inserted to meet the delay constraint. a high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look - up table is for buffer delay estimation. the experimental results show that the algorithm can efficiently achieve the trade - offs between number of buffers and delay, and avoid needless power and area cost. the running time is satisfactory
文摘:提出了在精確時延模型下，滿足時延約束的緩沖器數目最小化的演算法.給出一個兩端線網，該演算法可以求出滿足時延約束的最小緩沖器數目.運用高階時延模型計算互連線的時延，運用基於查找表的非線性時延模型計算緩沖器的時延.實驗結果證明此演算法有效地優化了緩沖器插入數目和線網的時延，在二者之間取得了較好的折中.演算法的運行時間也是令人滿意的When feature size comes to 0. 35 m, interconnect delay has contributed 70 % to total delay. distribution of delay parameters lies on actual implementation of layout, which results in the fact that timing closure has become the chief problem. so synthesis technology must be based on timing to insure timing closure
特徵尺寸進入0 . 35 m后，互連線延遲佔到系統延遲的70以上，而延遲參數的分佈又取決于版圖的具體實現，導致時序收斂成為設計的首要問題，因此綜合技術必須要基於時序，保證時序收斂。The internet is based on the sharing channel of tcp / ip protocol and consists of various heterogeneous subnets. it is unpredictable of its transportation latency, available bandwidth and data package lost rate. so it ' s necessary to have an efficient encoding method and an adaptive real time transportation strategy to meet the multimedia communication ' s requirement of latency and bandwidth
Internet基於tcp ip協議通道共享，由多種異構網路互連而成的，其中的傳輸延時、通道帶寬、數據包丟失率都是時變的、不可預測的，因此，對延時、帶寬要求很高的多媒體通信，必須有一種高效的編碼方法和根據帶寬變化的實時傳輸策略。Interconnection time delay
互連延時However, some improvements have been made for the distributed rc model, the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region. so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance. according to this model, two cases, that is, cmos driving transmission line and interconnect line between chips have been analyzed
對傳統的分佈rc模型進行了改善，但隨著互連向深亞微米級發展，寄生效應的影響尤其是電感的影響，必須考慮，因此建立新的rlc傳輸模型是很必要的，本文提出了這種新的互連模型，並對cmos驅動互連線和晶元之間互連兩種情況進行了分析，驗證了延時模型是可靠和精確的，並對延時的改善起到了指導作用。In this paper, several delay models have been provided and the results have been compared with the simulation to derive the accuracy of the models
本文就提出了簡單的rc延遲模型和復雜的rlc互連延時模型，將模型的結果與hspice模擬結果進行比較分析，驗證了模型能夠比較精確的計算延遲時間。Through the simulation and calculation of the delay models, the improvement degree of the new material and geometric parameters for the interconnect delay can be concluded and performance optimizations should be made by analyzing these influences
而通過互連延時模型的模擬與計算，得出新材料即銅和低k介質對延時的改善程度，及互連線的幾何參數對互連延時的影響，並根據這些確定最優尺寸來適應集成電路設計的需要。分享友人