數字邏輯系統 的英文怎麼說

中文拼音 [shǔzìluóxìtǒng]
數字邏輯系統 英文
dls digital logic system
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 統 : Ⅰ名詞1 （事物間連續的關系） interconnected system 2 （衣服等的筒狀部分） any tube shaped part of ...
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 邏輯 : logic
  • 系統 : 1. （按一定關系組成的同類事物） system 2. （有條理的;有系統的） systematic
  1. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. After the selection is made, the designer modifies his system digital circuit requirements to match the characteristics of the selected logic family.

    選擇好類型之後，設計人應該修改對系統數字電路的要求，以適應所選之邏輯電路參數。
  4. The thesis discusses on how to research and then design the led video panel system, which is a typical product of computer digital video system, by using the pld chip as the main control logic

    本論文討論用pld晶元作為主要控制邏輯來設計計算機數字視頻系統的一個典型應用型產品? ? led視頻電子顯示屏系統的研製方法。
  5. It is divided into port state control ( psc ) security check, flag state control ( fsc ) security check, ships quality appraisal, assistant business, report forms, the assurance of the target ship, electronic declare management, parameter design and purview management, the form design. the course of system implement is given in the thesis. the thesis emphasized to introduce the business logic of the psc security check and report forms 。 the implementation of pagestudio is detailed in the thesis

    深圳海事數字平臺分為港口國安全檢查（ psc ） 、船艦國安全檢查（ fsc ） 、船舶質量評價、輔助業務、報表、目標船的確定、電子申報管理、參數設計與權限管理、表單設計器9個功能模塊，在文中給出了系統開發環境搭建過程，並著重介紹了psc安全檢查與報表統計模塊的業務邏輯。
  6. The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit

    該系統硬體包括數字信號處理器晶元、前向輸入通道、液晶顯示器、模擬量輸出部分、鍵盤輸入部分、保護電路部分和邏輯控制部分。
  7. Main course : structure of network of structure of all of technology of principle of analysis of logic of technology of electron of circuit principle, imitate, number, number, computer, microcomputer, computer science department, computer, advanced language, assembly language, data, operating system

    主要課程：電路原理、模擬電子技術、數字邏輯、數字分析、計算機原理、微型計算機技術、計算機系統結構、計算機網路、高級語言、匯編語言、數據結構、操作系統等。
  8. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  9. And, the thesis mainly presents the research on the key technique of the dataflow control, including the realization of the pci interface control, the control of the sram memory that read or written by fpga, the pretreatment and the output control of the image and the intercommunication between pc and fpga. and then, it presents the design and the realization of the pc application program. in the end, it presents the debugging stepps and the application of the system.

    本文的重點在於介紹高解析度實時圖像處理系統的fpga控制邏輯設計，主要研究了該數字圖像處理系統中影響系統實時處理速度的數據流控制技術，如pci介面控制、 fpga與外部ram的高速讀寫控制、圖像的採集預處理，圖像的輸出控制等，本文還介紹了高解析度實時圖像處理卡的上位機應用程序設計與實現，本文的最後介紹了系統的調試及應用。
  10. With the rapid development of semiconductor, digital integrated circuit ( p, memory, standard logic gates, etc. ) and advance computer technology, the various measuring instruments ( virtual instruments ) with the powerful function of pc are produced in different industrial and scientific research fields. as we all known, the traditional instruments are usually built with discrete components and small scale ics, the disadvantages are obvious in system design, debugging and maintenance

    隨著半導體技術與數字集成電路（微處理器、存貯器以及標準邏輯門電路等）技術的迅速發展，特別是隨著計算機技術的發展，在工業生產和科學技術研究的各行各業中，人們利用pc機的強大處理功能代替傳統儀器的某些部件，開發出各種測量儀器（虛擬儀器） ，傳統儀器的數字邏輯部分多是採用分立集成電路（ ic ）組成，分立ic愈多，給系統的電路設計、調試及維護帶來諸多不便。
  11. This course consists of lectures and labs on digital logic, flipflops, pals, counters, timing, synchronization, finite - state machines, and microprogrammed systems

    本課包括了數字邏輯、觸發器、 pal （可編程邏輯陣列） 、計數器、時序、同步、有限狀態機、和微控制系統方面的講課與實驗。
  12. The hardware circuitry of the whole digital scan conversion system is realized through the complex programmable logic devices so as to improve stability, flexibility and real - time of the digital hardware circuitry. a high - performance digital scan conversion system is researched and developed

    整個數字掃描變換系統的硬體電路都使用復雜可編程邏輯器件實現，增加了數字電路系統的實時性、穩定性和靈活性，設計和實現了一種高性能的數字掃描變換系統。
  13. In order to mak neuha networ can deal with formuja, in thes theis, numenis sysem of pidpoihonal j, - iv calculus is proposed

    為使兩者的處理對象相一致，提出了命題邏輯系統的數字化，即尋找與命題邏輯系統戶完全同構的一個數字系統（
  14. 2. numerais system of propositional calculus nend netwrk deals with data, but it is a formula set in proposihonal calculus

    命題邏輯系統的數字化神經網路的處理對象是數據，而命題邏輯系統的處理對象是命題公式集。
  15. This article mainly discusses the enforcement rule and requirement of intelligent teaching system mode based on digital logic course ; discusses how to provide best tactics of teaching means and method by using digital logic course ' s intelligent teaching system ; and how to make use of intelligent teaching system ' s intelligent tools based on digital logic course, to teach digital logic course, so as to further improve teaching quality and teaching level

    文章主要探究了基於數字邏輯課程的智能教學系統模型的實施、規則和要求；探究了如何利用數字邏輯課程的智能教學系統提供最佳的教學手段和教學方法的策略，以及如何利用基於數字邏輯課程的智能教學系統的智能工具，對數字邏輯課程進行教學，以達到進一步提高教學質量和教學水平的目的。
  16. In this paper, the microwave ranger finder adopts two lattice 1016 pld chips to integrate some separate circuits and make the function simulation. it proves the isp chip may improve the stability of the system and may reduce the power consumption too

    同時由於在系統可編程邏輯器件的集成度不斷提高，可以在單片晶元中集成整個數字電路系統，使得系統的穩定性得到了提高，而且體積、功耗大大減小。
  17. However, the logic analysis instrument captures data rapidly and replays slowly and this mode goes against real - time processing, not to mention the real - time cooperation between digital signal generator and logic analysis instrument. thus more powerful high - speed digital testing instruments are needed

    但邏輯分析儀是採用快速捕捉，慢速回放處理方式，難以實現實時處理，更難以實現數字信號發生器和邏輯分析儀復雜的實時聯動配合，所以現代數字測試系統中需要功能更為強大的高速數字測試儀器。
  18. In this thesis, we would present theory research and its implementation about mpeg - 2 ts stream “ health ” check analyzer. a brief narration about the background of our research and its mean would be put in the beginning. and then we would analyze structure of ts stream and its definition in iso / iec 13818 - 1, data structure of system layer and mechanism of decode would be stressed in this section, later, we would introduce principles and methods of mal - function check in mpeg - 2 ts network, parameters being presented by etsi tr 101 290 would be emphasized in this part

    本文將對mpeg - 2ts碼流「健康」檢測儀的理論研究和數字電路設計作出如下介紹:本課題研究的時代背景及研究現狀和意義; mpeg - 2ts碼流的數據結構，在iso / iec13818 - 1中的定義和描述，其系統層的數據結構及解碼機理; mpeg - 2ts碼流在網路中故障檢測的原理和方法， etsitr101290規定檢測參數分類; mpeg - 2ts碼流「健康」檢測儀實現的總體方案，基於fpga的數字邏輯電路實現方案總體模塊劃分，模塊劃分的依據，模塊實現功能;總體方案的具體實現，幾個重要參數如pcr間隔及精度檢測，快速crc檢測等的實現;設計實現的驗證方法，典型參數檢測實現的驗證模型及驗證結果。
  19. Furthermore, the design rules of high - speed digital systems and their self - checking and testing techniques are summed up

    並結合工程實踐和大量應用文獻，總結了高速數字邏輯系統的設計準則，以及高速數字系統的自檢和性能測試方法。
  20. Like reiserfs, xfs uses a logical journal ; that is, it does not journal literal filesystem blocks like ext3, and instead uses an efficient on - disk format to log metadata changes

    象reiserfs一樣， xfs使用邏輯日誌；即，它不象ext3那樣將文字文件系統塊記錄到日誌，而是使用一種高效的磁盤格式來記錄元數據的變動。
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