時序電路 的英文怎麼說

中文拼音 [shíxùdiànlù]
時序電路 英文
sequence circuit
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Optimize synchronous sequential circuit with retiming was introduced by leiserson and saxe in 1983, and retiming optimizational algorithm was summarized comprehensively in 1991

    Leiserson和saxe於1983年提出了利用重定時優化同步時序電路，並於1991年對重定時優化演算法做了全面的總結。
  2. Verification of sequential circuit design based on obdd

    時序電路設計的驗證
  3. Asynchronous sequential circuit

    異步時序電路
  4. Autonomous sequential circuit

    自激時序電路
  5. The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits

    本文的研究內容正是面向非掃描同步時序電路的并行atpg演算法。
  6. Most of vlsi circuits are sequential circuits. sequential circuits can be simulated by symbolic finite state machine ( fsm )

    Vlsi系統中大部分是時序電路，時序電路可以用符號化的有限狀態機（ finite - state - machine ，簡稱fsm ）來模擬。
  7. Although some scholars have done lots of work on the test generation of the digital circuits, it is still a well - known puzzle to test sequential circuits

    雖然各國學者在數字電路測試生成上已做了大量的工作，時序電路的測試生成仍然是公認的難題。
  8. The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations, which resulted in the complexity of the sequential circuit

    在高速時鐘和低速時鐘的情況下，系統有不同的時序要求，這就決定了時序電路的復雜性。
  9. The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm, and the results are better than other algorithms "

    採用國際標準時序電路iscas 』 89 （包括addendum 』 93 ）進行了演算法驗證，取得了優于文獻中其它演算法的結果。
  10. The logic design of sequence circuit of welding supply based on gal

    的焊接電源時序電路設計
  11. Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design

    在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。
  12. Research on the test technology of sequential logic circuits in the control system of magnetic bearings of hard disk drives

    磁懸浮硬盤轉子控制系統中時序電路測試技術
  13. Flip - flop is the core of sequential circuits, this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices, the jk flip - flop has strong function and high speed, and also riches the types of flip - flops in quantum circuits

    所設計的jk觸發器功能強，且與傳統的觸發器相比，基於rt量子器件的邊沿型jk觸發器具有量子器件的功耗低、速度快、電路簡單等特點。本文設計的jk觸發器豐富了量子電路中觸發器的種類，使得量子時序電路的設計更為靈活。
  14. In such situation, controlling of the transf - orming process and synchronizing of sampled data only could be achie - ved via hardware, and data must be stored ( by using high - speed stora - ge chip ) and digital signal must be processed ( by using high - speed d - sp ) in real time simultaneously

    在這種情況下，通常只能用硬體實現轉換過程的控制和采樣數據的同步，仔細設計時序電路，同時必須採用高速存儲晶元對數據進行存儲和高速的數字信號處理器（ dsp ）完成數字信號的實時處理。
  15. Automatic water - measuring meter is the combinative production of traditional method and present cmos integration circuit technology. it consists of water - level sensor and mainframe circuit. on the basis of analyzing its application, this paper gives the design of mainframe circuit, including time circuit, time - sequence circuit, input - interface circuit, switch circuit and power circuit

    本文在分析cmos集成電路應用的基礎上，給出了自動量水儀表主機電路的設計，包括定時電路、時序電路、輸入介面電路、開關電路和電源電路的設計；其次，對水位傳感器進行了研究，分析了水位傳感器的工作原理、測量使用條件、動態特性、靜態特性以及水位傳感器的率定、標定方法。
  16. But circuitry net table which is synthesized by synthesizer is not necessarily achieve the demand of designer, so aim for the speed demand of destination, the sequence circuit which is synthesized demand speed optimization

    但是由於綜合器綜合得到的電路網表不一定能達到設計者的設計要求，所以需針對給定的速度要求，對綜合得到的時序電路進行速度優化。
  17. Its innovation is to extend existed fanout - free region pwtitioning methods of combinational circuits to synchionous sequentia1 circuits, and combines fanout source fault simulation and critical path tracing. experimental resu1ts reveal that the efficiency of it is better than that of generic word - level fault parallel fs algorithms

    該演算法的創新在於擴充了現有的組合電路無扇出區劃分方法，使之對時序電路適用，並把它與扇出源故障并行模擬和臨界路徑追蹤方法相結合。
  18. The risky phenomenon of the electric potential sequential asynchronous circuit

    電位異步時序電路的冒險現象
  19. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  20. The automatic test vector generation method based on fault simulation is described, and the whole procedure of atpg of sequential circuits is analyzed, fault simulator - hope as an example

    本文闡述了基於模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。
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