時鐘型 的英文怎麼說

中文拼音 [shízhōngxíng]
時鐘型 英文
clock type
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops

    為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。
  2. The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.

    你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關系。
  3. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  4. Use low - density aluminum alloy oxide to the first, with the introduction into superior performance ; neiqiang use special vocabulary design let s hear first from the surface temperature is equipped with colour sets, enabling patients to feel comfortable ; pipeline grey colour black red light green light blue pink sea blue purple yellow note : 220 - tone models of the length of 52cm diameter listen first bamboo : 48mm film - based 30mm bell type

    採用低密度的鋁合金氧化聽頭，具有優越的導音性能;內腔採用特殊的圓弧設計，且聽頭表面都配有彩色的隔溫套，能使病人使用時感到舒適;管道顏色黑色灰色紅色深藍粉紅淺藍深綠淺綠海藍紫色黃色注：型號220導音管長度52cm聽頭外圓直徑： 48mm膜型30mm鐘型
  5. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  6. The main research contents of this dissertation are shown in the following : ( 1 ) introduce one method of use the counting pulse to develop ie measuring system and new method of using the high frequency clock signal to divide the space pulse

    本文主要研究內容如下: （ 1 ）系統論述了一個脈沖計數方式的ie測量系統的測量原理，闡述了一個採用高頻的時鐘信號細分空間脈沖的新型細分方法。
  7. Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout

    本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。
  8. Gears for instruments and clockwork mechanisms - cycloidal type gears - double circular arc type gears

    儀器和時鐘機構裝置用齒輪.第2部分:擺線齒輪.雙環弧型齒輪.補充件no . 1
  9. The current models have phased out the g3 but continue to use the similar g4, both 32 - bit chips, running at various clock speeds ; the recently introduced g5 is a 64 - bit ibm chip that mostly adds some multimedia - specialized instructions to the power4 chip models

    當前的g3型已經逐步被淘汰，取而代之的是類似的g4型，它們都是32位晶元，運行於不同的時鐘脈沖速度下；最近推出的g5是一款64位ibm晶元，主要是向power4型晶元中添加了一些多媒體專用指令。
  10. The following is main content of our thesis. the first, we analyze the system operation theory of cmos image sensor with pixel level adc ( a / d converter ). it is made up of three sections : pixel array, clock signal generator and sam ( sequential access memory )

    本文的主要內容如下：首先，我們對像素級a d轉換型圖像傳感器的系統工作原理進行了分析，是由像素陣列、時鐘信號產生器和sam （順序讀寫存儲器）三部分構成的。
  11. The ip core is made up of four modules, which are alu _ module, control _ module, timer _ module and port _ module

    這個ip模型主要由運算器模塊，控制器模塊，時鐘模塊和埠模塊四個部分組成。
  12. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。
  13. And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed

    本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。
  14. In the designed hardware, at89c51 single chip computer and many kinds of new type circuit chip ( including : special power measuring chip - cs5460a, ds1302 calendar / clock chip, sms0601 lcd, x5045 serial memory ) are used for design. the hardware circuit is simplified, the meter ' s anti - interference ability is enhanced and the precision of measurement is also advanced

    設計中以at89c51單片機為核心，採用多種新型集成電路晶元（包括電能計量專用晶元cs5460a 、 ds1302日歷時鐘晶元、 sms0601液晶顯示器、 x5045串列存儲器）進行介面設計，簡化了硬體電路，提高了電能表的抗干擾能力和測量精度。
  15. Some typical machine attributes include the amount of memory, cpu type, cpu clock speed, and current machine load

    典型的機器屬性包括內存數量、 cpu類型、 cpu時鐘速度以及當前的機器負載。
  16. The programmable logic device ( pld ) is applied in this system for controller as well as data storage

    本系統採用鎖相型頻率合成器作為超高速模數轉換器的時鐘源。
  17. It introduces by form the conception of event - clock automata and two - way timed automata, it gives the construction from event - clock automata to two - way timed automata and it proves the inclusion relationship between them

    基於時間自動機不同模型的驗證被工業界廣泛應用，本文形式描述了兩種這樣的模型，給出了從事件時鐘自動機到雙向時間自動機的構造方法，證明了二者識別語言之間的包含關系。
  18. In addition, an experimental system using c language is established, including modules such as representation of waveform polynomial, decision of path senstization, delay computing, clocking based on single - period sensitization, clocking based on multi - period sensitization, test generation considering noise and transformation from bit - level waveform polynomial to word - level polynomial model. they respectively used to test models and techniques proposed in this paper

    另外， :基於c語言本人設計開發了一個實驗軟體系統，該系統包括波形多j一貞式表示模塊、敏化通路判定模塊、延時計算模塊、單周期敏化的最小時鐘周期精確確定模塊、多周期敏化的最小時鐘周期確定方法模塊、考慮噪聲的測試生成模塊和位級波形多項式描述轉化成字級多項式描述模塊，分別用於對本文各章中提出的自動化設計的模型和方法進行實驗驗證。
  19. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  20. The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed

    在此基礎上設計了基於scc準同步的一種時鐘恢復實現電路和兩種字元型起止式同步電路（實現了一種） 。設計了正碼速調整技術中快慢時鐘的三種控制電路。
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