時鐘比較器 的英文怎麼說

中文拼音 [shízhōngbǐjiàoqì]
時鐘比較器 英文
clock comparator
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 比 : Ⅰ動詞1 （比較; 較量高下、 長短、距離、好壞等） compare; compete; contrast; match; emulate 2 （比...
  • 較 : Ⅰ動詞1 （比較） compare 2 [書面語] （計較） dispute Ⅱ副詞（比較） comparatively; relatively; fair...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 比較 : 1 （對比） compare; compare with; contrast; parallel （with）; comparison; by comparison; in comp...
  1. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  2. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  3. The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter

    整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。
  4. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown

    調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。
  5. Consequently, based on the analysis of quad el transceiver working principle and the comparison of various processors " features, the author proposes the hardware design of quad el transceiver, and then introduces the time module, interface circuit of the system, storage system module, four channel el composer module, cpu module and time - interval exchange module respectively

    然後，在分析了四路e1收發器的工作原理和比較了各類處理器特點的基礎上，提出了四路e1收發器的硬體設計，分別介紹了時鐘模塊、系統介面電路、存儲系統模塊、四通道e1合成器模塊、 cpu模塊以及時隙交換模塊。接著，在研究分析了g
  6. Rc and other relaxation oscillators just will not do since amplitude noise in whatever circuit functions as a comparator will appear as phase noise on the output signal

    Rc諧振器以及其它一些張弛振蕩器不能滿足要求，這是因為它們的核心是電壓比較器，需要利用電壓信號的波動（噪聲）來獲得穩定的輸出，這種波動就構成了時鐘的抖動。
  7. The new, energy - saving and efficient light source need efficient controllers to drive, however, because of their own complex identity, metal halide lamps is activated more difficult. especially when the lights work time, it need to wait 5 ~ 10 minutes before re - lit. the activate and re - activate features in some areas is restricted

    新型、節能、高效的光源需要高效率的控制器來驅動，然而，金屬鹵化物燈由於其自身的復雜特性，啟動比較困難，特別是當燈工作一段時間，關斷后需要等待5 10分鐘才能重新點亮，它的這種啟動和再啟動特性在一些工程領域受到了限制。
  8. By careful selection of the ratio between this resistor and the integrating resistor ( a few tens of ohms in the recommended circuit ), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. 3

    通過小心選擇這個電阻和積分電阻之間的比值（在推薦線路里，大約是數十歐姆） ，比較器的延遲就可能被補償，最大的時鐘頻率可近似延伸到3 . 3倍。
  9. In order to make full behavior simulation of sigma - delta modulator, the noise models have been set, taking into account most of the sigma - delta modulator ’ s non - idealities and the final result supports the noise models. last, the main circuits of modulator have been designed, such as operational amplifier, comparator and clock generator, the design principle of noise - killed logic circuit has been presented. these circuits have been simulated

    調制器的噪聲模型，考慮了影響調制器性能的一些主要非理想因素，通過模擬驗證了噪聲模型的正確性;最後，設計實現了結構中的主要電路，如運放、比較器、時鐘產生電路，闡述了噪聲抵消邏輯電路的工作原理，利用hspice和cadencespectre對各電路進行了模擬，驗證其功能。
  10. Then the author presents the structure and the working principle of digital loop carrier system, in other word, the application environment of quad el transceiver, and then the author highlights the role that quad el card plays in the whole system, consequently, the author introduces the systematical structure and features of arm embedded processor. concerning about the restrict requirement of time during data transmission, the author of this paper also introduces the fpga technology, which is used mainly for providing the system with accurate time

    接著敘述了數字環路系統的結構和工作原理，即四路e1收發器的應用環境，著重介紹了四路e1板卡在整個系統中所扮演的角色和嵌入式處理器arm的體系結構和特點，鑒于數據傳輸中對時鐘的要求比較嚴格，本文還介紹了fpga技術，應用它主要是為系統提供各個精確的時鐘。
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