柵電導 的英文怎麼說

中文拼音 [zhàdiàndǎo]
柵電導 英文
gate conductivity
  • 柵 : 柵名詞（柵欄） railings; paling; palisade; bars
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 導 : 動詞1. （引導） lead; guide 2. （傳導） transmit; conduct 3. （開導） instruct; teach; give guidance to
  1. This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n-type.

    這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的P型襯底轉變成N型。
  2. The factors limiting the frequency band of the wide - band amplifier are introduced. through analyzing the effects of the intrinsic parameters and parasitical on the frequency characteristics, a method of improving fr of mosfet by using short channel device and making mosfet work at the saturation region through raising vgs is put forward ; the effects of different kinds of circuit configurations on the frequency characteristics and the junction voltage on the voltage pattern circuit, current pattern circuit and frequency characteristics are analyzed. according to the linear theory of transconductance which is applied in the bit circuit, the current pattern amplifier circuit, current transfer circuit and output circuit which consist of mosfet and the wide - band amplifier composed of them are put forward

    介紹了限制寬帶放大器頻帶寬度的因素，通過分析mosfet的本徵參數、寄生參數對頻率特性的影響，提出了採用短溝器件、使mosfet工作在飽和區、抬高柵源電壓等提高mosfet特徵頻率的方法；分析了不同電路組態對放大器頻率特性的影響、節點電壓對電壓模電路、電流模電路頻率特性的不同影響，根據應用於雙極晶體管電路的跨導線性原理，提出了採用mosfet構成的電流模放大電路、電流傳輸電路、輸出電路以及由它們所組成的寬帶放大器，獲得了良好的頻率響應。
  3. The enterprise wenglor sensoric elektronische geraete gmbh is well - known and engaged not only in tettnang, but also in the specialized industries of its sphere of activity, with plastic light guidance cable, light screems, color sensors and at the same time with one - way light barrier, printers ' imprint scanner and knitting and drafting machines, mesh - making machines a competent partner

    Wenglor sensoric elektronische geraete gmbh是一家現代化的、可靠的專門產品供應商，這家供應商從事條形碼讀取儀器，印刷商標讀取器，單向光柵，色彩感應器，光澤敏感元件、光澤傳感器，塑料光導電纜，光柵，光傳導線纜，光勢壘、光電裝置對、光電柵欄，事故維護光柵，來復式卡釬、圓規，鏡面反射箱，傳感技術，編織、針織機，網路生產機械的製造、銷售。
  4. Because massive harmonic interference in the electrical network, it causes signal - sampling to include the very big harmonic in the measurement system, for eliminating measurement result influence by harmonic, the paper has an in - depth study of fourier transformation harmonics analysis measurement principle, analysis the forming reasons of frequency spectrum leakage and railing effect during measurement, achieves phase locked loop and frequency multiplier technique to realize integer - period synchronous sampling and eliminate impact of frequency spectrum leakage and railing effect in the result of measurement, and investigates in depth theory on phase locked loop and frequency multiplier technique, gives the method of realizing phase locked loop and frequency multiplier technique

    由於電網中存在大量的諧波干擾，導致測量系統中取樣信號也含有很大的諧波，為了消除諧波對測量結果的影響，論文深入研究了傅立葉變換諧波分析法的測量原理，分析了測量中頻譜泄漏和柵欄效應形成的原因，提出了採用鎖相環倍頻技術實現信號的整周期同步采樣，消除頻譜泄漏和柵欄效應對測量結果的影響，並對鎖相環倍頻技術的理論進行了深入研究，給出鎖相環倍頻技術的實現方法。
  5. These problems boost the study of high - k materials as the alternatives of sio2 gate dielectrics. among all high - k gate dielectric materials, hafnium oxide ( hfo2 ) is being extensively investigated as one of the most promising candidate materials due to its superior thermal stability with poly - si, biggish constant and reasonable band alignment. our researches focus on hfo2 dielectrics

    高k柵介質材料已經被廣泛地研究來替代sio _ 2 ，以降低柵泄漏電流和改善可靠性，其中， hfo _ 2由於其較大的介電常數、較大的禁帶寬度、與si的導帶和價帶較大的偏置、以及與si的高的熱力學穩定性等特徵，被認為是最有希望的替代sio _ 2的柵介質材料之一。
  6. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高
  7. Then, establish electric field and magnetic field matching equation of space and plate wave - guide. program about slice - grating - circular polarization. analyse its transmit characteristic and polarization characteristic

    然後運用單極模匹配方法建立空間場和平板波導場的電場和磁場匹配方程，編制分析薄片型光柵圓極化器的程序，得到模擬結果。
  8. The main work of this thesis analyzes the organic static induction transistor ' s operational mechanism, and researchs the change of gate length, change of gate - drain distance and change of electric channel breadth for operational characteristics influence of organic static induction transistor

    本論文的主要工作是解析有機靜電感應三極體的工作機理，並研究了柵極長度變化、柵漏極間距變化和導電溝道的寬度變化對有機靜電感應三極體工作特性的影響。
  9. This thesis in combination with the actual engineering demand, analyzes and designs a horizontally polarized triangular - grid planar phased array antenna, which composed of open - ended rectangular waveguide, the main steps of analyzing and designing are as follows : 1. at first, taking no account of mutual coupling among the array elements, classical electromagnetic theory is used to establish analyzing model for finite array, and initial value parameters of the array structure which basic satisfy the design index are got, these parameters provide reference for subsequent analyzing and design

    本論文結合實際工程需要，分析和設計了一個採用水平極化方式的三角形柵格矩形波導相控陣天線，其主要步驟如下: 1 .首先，在不考慮陣列單元間互耦影響的情況下，採用經典電磁理論建立有限陣列分析模型，通過分析得到了基本滿足設計指標的陣列結構參數，為后續的分析、設計提供參考。
  10. Secondly, the transient characteristics of fn tunneling and hot hole ( hh ) stress induced leakage current ( silc ) in ultra - thin gate oxide are investigated respectively in this dissertation

    其次，本文分別研究了fn隧穿應力和熱空穴（ hh ）應力導致的超薄柵氧化層漏電流瞬態特性。
  11. The first step is the creation of trap centers in ultra - thin gate oxides by hot electron injection, and the second step is oxides breakdown induced by hole trapping

    首先注入的熱電子在超薄柵氧化層中產生陷阱中心，然後空穴陷入陷阱導致超薄柵氧擊穿。
  12. This dissertation is the first report that points out the cooperation of hot electron and hole is essential for the tddb of ultra - thin gate oxides

    首次提出了超薄柵氧化層的經時擊穿是由熱電子和空穴共同作用導致的新觀點。
  13. The first important thin film from the thermal oxide group is the gate oxide layer under which a conducting channel can be formed between the souce and the drain

    第一個重要的來自熱氧化組薄膜是柵氧化層，在它之下，源和漏之間就能形成導電通道。
  14. We have made three - dimension electric conduct grid by hand and we have successfully used it as anode grid in lead - acid battery. this kind of three - dimension electric conduct grid can improve the utilization of pam by 7 - 9 % in different discharge current density and can reduce the plate electrochemical impedance to one tenth of the normal plate. also this kind of grid can improve the marginal reaction current density in a certain degree

    我們通過手工製作了三維導電體板柵，並成功的應用於電池的正極作為正極的板柵，這種三維導電體板柵能夠在各種不同的放電電流密度下提高正極活性物質利用率7 9 ，能夠使電池正極板的電化學阻抗降低到普通板柵的1 10左右，使正極板的極哈爾濱j _程大學碩十學位論文限反應電流密度略有所提高，但是這種板柵的耐腐蝕性能很不理想，使得所製作電池的壽命很短。
  15. With the research on hfoxny gate dielectrics, it can reduces leakage current and increase crystallizing point ; our research can help to realize the leakage current mechanism and silc effect of hfo2, futher more it can offer us direction on optimize the fabrication process

    結果表明，與hfo :相比，氮化的hfo :具有小的漏電流。我們的研究結果有助於進一步了解hro :柵介質的泄漏電流機制和silc效應的特徵，為進一步優化hfo :高k柵介質的制備工藝提供指導。
  16. We researched fabrication at different asputtering and annealing atmosphere, the different process conduced different electrical properties. we can conclude a higher annealing temperature and higher proportion of o2 during reactive sputtering favors the improvement of electrical performances of hfo2 dielectrics ; 4. the analysis of i - v curves of these devices displays different leakage current mechanism under different area of applied bias - voltage ; as to silc. there are different leakage current mechanism at influence of sil. c ; 5

    研究表明，在優化工藝條件下制備的hfo _ 2介質層中，襯底注入條件下由於其較低的體和界面缺陷密度，漏電流的輸運機制主要以schottky發射為主; silc效應導致hfoz / si界面缺陷態的增加，從而使得襯底注入條件下，柵泄漏電流機制不僅有schottky發射還有f一p發射機制起主要作用; 5 ）初步研究了氮化的hfo : （ hroxny ）柵介質的電學特徵。
  17. By studying and using conventional 1c process in combination with electron beam lithography ( ebl ), reactive ion etching ( rie ) and lift - off process, several efficient results are produced : semiconductor and metal nano - structures are fabricated ; the matching problem of photolithography and electron beam lithography is well solved ; the process efficiency is improved ; the process is offered for the controlled fabrication of nano - structures by repetitious process testing ; several nano - structures such as si quantum wires, si quantum dots, double quantum dot structures and tri - wire metal gate are firstly fabricated by using ebl and rie processes

    研究利用常規的硅集成電路工藝技術結合電子束光刻，反應離子刻蝕和剝離等技術制備半導體和金屬納米結構，很好地解決了普通光刻與電子束光刻的匹配問題，提高了加工效率，經過多次的工藝實驗，摸索出一套制備納米結構的工藝方法，首次用電子束光刻，反應離子刻蝕和剝離等技術制備出了多種納米結構（硅量子線、量子點，雙量子點和三叉指狀的金屬柵結構） 。
  18. The thesis has done the widespread investigation and study to the domestic and foreign ’ s technologies of analogy low voltage and low power, and analyzes the principles of work, merts and shortcomings of these technologies, based on the absorption of these technologies, it designs a 1. 5v low power rail - to - rail cmos operational amplifier. when designing input stage, in order to enable the input common mode voltage range to achieve rail - to - rail, it does not use the traditional differential input pair, but use the nmos tube and the pmos tube parallel supplementary differential input pair to the structure, and uses the proportional current mirror technology to realize the constant transconductance of input stage. in the middle gain stage design, the current mirror load does not use the traditional standard cascode structure, but uses the low voltage, wide - swing casecode structure which is suitable to work in low voltage. when designing output stage, in order to enhance the efficiency, it uses the push - pull common source stage amplifier as the output stage, the output voltage swing basically reached rail - to - rail. the thesis changes the design of the traditional normal source based on the operational amplifier, uses the differential amplifier with current mirror load to design a normal current source. the normal current source provides the stable bias current and the bias voltage to the operational amplifier, so the stability of operational amplifier is guaranteed. the thesis uses the miller compensate technology with a adjusting zero resistance to compensate the operational amplifier

    本論文對國內外的模擬低電壓低功耗技術做了廣泛的調查研究，分析了這些技術的工作原理和優缺點，在吸收這些技術成果基礎上設計了一個1 . 5v低功耗軌至軌cmos運算放大器。在設計輸入級時，為了使輸入共模電壓范圍達到軌至軌，不是採用傳統的差動輸入結構，而是採用了nmos管和pmos管並聯的互補差動輸入對結構，並採用成比例的電流鏡技術實現了輸入級跨導的恆定;在中間增益級設計中，電流鏡負載並不是採用傳統的標準共源共柵結構，而是採用了適合在低壓工作的低壓寬擺幅共源共柵結構;在輸出級設計時，為了提高效率，採用了推挽共源級放大器作為輸出級，輸出電壓擺幅基本上達到了軌至軌;本論文改變傳統基準源基於運放的設計，採用了帶電流鏡負載的差分放大器設計了一個基準電流源，給運放提供穩定的偏置電流和偏置電壓，保證了運放的穩定性;並採用了帶調零電阻的密勒補償技術對運放進行頻率補償。
  19. The chip is accomplished in the full cooperation with other team members, the author pays particular attention to the analysis of the whole chip architecture and three sub - block design : transconductance amplifier ( ota ), voltage reference and current reference. based on existed technologies, a new high order temperature compensated voltage reference and a creative current reference with high order temperature compensation are shown respectively. the author simulated all the sub - block and whole chip by hspice

    該晶元的設計是由小組成員共同完成，本人主要負責了總體電路的分析、聯合模擬驗證及以下三個子電路的設計: 1 、跨導放大器，詳細分析了bandgap跨導放大器輸入級的動靜態特性及其優缺點，並結合系統要求，設計了一種與cmos工藝相兼容、可替代bandgap跨導放大器的低壓共源共柵跨導放大器。
  20. My paper presents us the theory of polarization duplexing grid with the high power microwave input. first, the new field of hpm has been introduced. then comes the principle of polarization duplexing grid

    本論文就極化雙工柵在理論上做了一個研究? ?對極化雙工柵電磁場特性的數值分析方法進行了理論推導，並編制了計算程序，為高功率微波下的極化雙工柵的設計提供了理論依據和計算程序。
分享友人
分享到 Line

分享到臉書