溝道效應 的英文怎麼說

中文拼音 [gōudàoxiàoyīng]
溝道效應 英文
channel effect
  • 溝 : 名詞1 （挖掘的水道或工事） channel; ditch; gutter; trench 2 （淺槽;似溝的窪處） groove; rut; furr...
  • 道 : Ⅰ名詞（道路） road; way; route; path 2 （水流通過的途徑） channel; course 3 （方向; 方法; 道理） ...
  • 效 : Ⅰ名詞（效果; 功用） effect; efficiency; result Ⅱ動詞1 （仿效） imitate; follow the example of 2 ...
  • 應 : 應動詞1 （回答） answer; respond to; echo 2 （滿足要求） comply with; grant 3 （順應; 適應） suit...
  • 效應 : [物理學] effect; action; influence
  1. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高
  2. We represent a temperature model of surface carrier mobility of short channel most after thinking about kinds of dispersion effect

    在考慮了各種散射效應對遷移率的影響后，提出了短溝道most表面載流子遷移率的溫度模型。
  3. To minimize channeling effects, the gaas target should be misaligned from the axis of the beam.

    為了使溝道效應最小，GaAs靶應稍偏離離子束的軸向。
  4. In the topic 1, utilizing the natural lysimeters and drainage region in wudaogou station, based on expriment and imitation methods, frist the hydrology effect of drainage has been analyzed, and then the index of water logged farm drainage and suitable ground water level have been provided. on the theory of darcy rule and farm hydrodynamics, the standard and pattern and empirical formula of farm drainage system have been presented as well, and provide scientifically foundation for drainage planning

    在農田排水技術研究中，利用五道溝實驗站地中蒸滲儀和排水試驗區，採用試驗法和動態模擬法，分析了排水工程的水文效應，提出了農田排漬標準和作物適宜的地下水位埋深，採用達西定律和農田水動力學原理，提出了農田排水系統的規格、布置方式及經驗公式，為排水工程規劃提供依據。
  5. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs146

    半導體分立器件. cs146型硅n溝道耗盡型場效應晶體管.詳細規范
  6. Semiconductor discrete device. detail specification for type cs141 silicon n - channel mos deplition mode field - effect transistor

    半導體分立器件. cs141型硅n溝道mos耗盡型場效應晶體管詳細規范
  7. Semiconductor discrete device. detail specification for type cs140 silicon n - channel mos deplition mode field - effect transistor

    半導體分立器件. cs140型硅n溝道mos耗盡型場效應晶體管.詳細規范
  8. Semiconductor discrete device. detail specification for type cs5114 cs5116 silicon p - channel deplition mode field - effect transistor

    半導體分立器件. cs5114 cs5116型硅p溝道耗盡型場效應晶體管詳細規范
  9. Semiconductor discrete device. detail specification for type cs4091 cs4093 silicon n - channel deplition mode field - effect transistor

    半導體分立器件. cs4091 cs4093型硅n溝道耗盡型場效應晶體管詳細規范
  10. Semiconductor discrete device. detail specification for types cs4856 cs4861 silicon n - channel deplition mode field - effect transistor

    半導體分立器件. cs4856 cs4861型硅n溝道耗盡型場效應晶體管詳細規范
  11. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs1 gp, gt and gct classes

    半導體分立器件gp gt和gct級cs1型硅n溝道耗盡型場效應晶體管.詳細規范
  12. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs4. gp, gt and gct classes

    半導體分立器件gp gt和gct級cs4型硅n溝道耗盡型場效應晶體管.詳細規范
  13. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs10. gp, gt and gct classes

    半導體分立器件gp gt和gct級cs10型硅n溝道耗盡型場效應晶體管.詳細規范
  14. In order to investigate the effect of high - field hot - carrier on devices and circuits, the electrical stress experiment is carried out with 1. 2 n m, 1. 0 n m and 0. 8 u m channel length home - made mosfet ' s by the monitor system with ate and cat technology. by using the fresh and degraded experiment data, bsim2 model parameters are extracted

    為了分析研究高場熱載流子效應對器件和電路特性可靠性的影響，採用自動測試與cad技術相結合的監測系統，對國內溝道長度1 . 2 m 、 1 . 0 m和0 . 8 m的mosfet進行了電應力退化實驗，並根據實驗結果提取了退化前後器件的bsim2模型參數。
  15. Under high drain voltage condition, the results proved that channel electrons are easily ejected into gan buffer layer and be trapped to induce current collapse

    在大漏極電壓條件下，溝道電子易於注入到gan緩沖層中，並被緩沖層中的陷阱所俘獲，耗盡二維電子氣，從而導致電流崩塌效應。
  16. This paper chooses bsim3 ( berkeley short - channel igfet model ) the model to be extracted, which is for short channel mos field effect transistor specially. these works are presented in this paper. 1

    本論文選取目前業界佔主流地位的bsim3 （ berkeleyshort - channeligfetmodel ）為將要提取的模型，它是專門為短溝道mos場效應晶體管而開發的一種模型。
  17. The source drain extension ( sde ) structure and its reliability are thoroughly studied. first, it is shown that the sde structure can suppress short channel effect effectively and the parasitic resistance at the sde region has an effect on performance. it is proposed that increasing the dose condition in the sde region can reduce the parasitic resistance and should be adopted to achieve high performance for deep submicron devices

    本文對深亞微米源漏擴展mos器件結構及其可靠性進行了深入研究，首先通過模擬驗證了源漏擴展（ sde ）結構對短溝道效應的抑制， sde區寄生電阻對器件性能的影響以及sde區摻雜濃度的提高對器件性能的改善，指出了器件尺寸進一步減小后，提高源漏擴展區摻雜濃度的必要性。
  18. The model of threshold voltage solves the problems of nonuniformly doped channel, short channel effect, implantation for adjusting threshold voltage, edge capacitance of gate, etc. not only the model can be used in ldmos, but it can perfectly describe the short channel effect of threshold voltage for all other mos devices

    其中，閾值電壓模型解決了溝道非均勻摻雜、短溝道效應，調閾值注入，柵邊緣電容等問題。該模型不僅適用於ldmos ，也可以很好地描述所有的mos器件閾值電壓的短溝道效應，嚴格證明了短溝道效應會引起閾值電壓的減小。
  19. This paper also presented the structure of soi bjmosfet and discussed and analyzed the advantages of this device by comparing with the bulk bjmosfet. its advantages are as fellow : no latch - up effect, better capability of resisting invalidation, much smaller parasitic capacitance, weaker hot - carrier effect and short - channel effects, and simpler technics, and so on

    通過與體硅bjmosfet比較，討論和分析了soibjmosfet的優點：無閂鎖效應、抗軟失效能力強、寄生電容大大降低、熱載流子效應減弱、減弱了短溝道效應、工藝簡單等。
  20. To minimize channeling effects, the gaas target should be misaligned from the axis of the beam

    為了使溝道效應最小， gaas靶應稍偏離離子束的軸向。
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