熱載子 的英文怎麼說

中文拼音 [zǎizi]
熱載子 英文
hot carriers
  • : 載Ⅰ名詞(年) year : 一年半載 six to twelve months; six months to a year; 三年五載 three to five ...
  • : 子Ⅰ名詞1 (兒子) son 2 (人的通稱) person 3 (古代特指有學問的男人) ancient title of respect f...
  1. The tendency for the magnetic carriers to become aligned is completely offset by their thermal energy.

    磁性排列的趨勢完全被它們的能所抵消。
  2. Device degradation behaviors of typical - sized n - type metal induced lateral crystallized polycrystalline silicon thin film transistors were investigated under two kinds of dc bias stresses : hot carrier stress and self - heating stress

    本文主要研究了典型尺寸的n型金屬誘導橫向結晶多晶硅薄膜晶體管在兩種常見的直流應力偏置下的退化現象:退化和自加退化。
  3. Reviews building load - estimating procedures to ensure that proper loads are used to size the ground - source subsystems

    還有評估建築物冷/,從而選用恰當的地源系統。
  4. Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet

    基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析,對所得結果從器件內部物理機制上進行了討論,最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深(凹槽深度)的增大,槽柵器件的閾值電壓升高,亞閾斜率退化,漏極驅動能力減弱,器件短溝道效應的抑制更為有效,抗性能的提高較大,且器件的漏極驅動能力的退化要比改變結深小.因此,改變槽深加大負結深更有利於器件性能的提高
  5. Account for the high electrical field induced from the high applied voltage relative to small dimension device, the mechanism of hot - carrier generation is analysed, the si - h bond broken model for hot - carrier injection and interface states generation is deduced and the substrate current model is developed

    基於mosfet偏壓不能按比例縮小所導致的高電場,對mosfet的產生機理進行了分析,導出了注入所引起的界面態的si - h健斷裂模型,並建立了表徵器件效應的襯底電流模型。
  6. A new hot - carrier - induced tddb model of ultra - thin gate oxide is reported in this dissertation

    本文提出了一個全新的增強的超薄柵氧化層經時擊穿模型。
  7. It is proposed that the higher dose condition creates more hot carriers but the lower sensitivity to hot carrier effect. therefore, the optimum dose for reliability is determined from the trade - off between the above two aspects. finally, a simple model is proposed and discussed

    本文還深入研究了sde區摻雜濃度對器件可靠性的影響,指出濃度的提高雖然會產生更多的,但由於其對損傷的敏感度降低,因此將存在一種折衷,最後通過一個簡單的寄生電阻模型,對摻雜濃度提高后,器件對損傷敏感度降低的現象做出了很好的解釋。
  8. Hot - carrier induced oxide breakdown shows different characteristics compared with that induced by conventional fn stress

    與通常的fn應力實驗相比較,導致的超薄柵氧化層擊穿顯示了不同的擊穿特性。
  9. Therefore, the solution to the hot - carrier degradation of mos circuits is obtained. the other hot - carrier immunity techniques such as

    對抗退化的mos器件lddnghtlydopeddrain )結構及柵氧化層加固技術也作了簡單的介紹。
  10. So, both 1 / f noise power spectrum measurement and similarity coefficient extracted from its time series can offer economical, effective and indestructible tool to detect the latent damage induced by esd and hci for mosfets

    因此,無論是1 / f噪聲功率譜的測試還是由其時間序列提取得到的相似系數均可以作為經濟、有效、完全非破壞性的工具,替代傳統的電特性用於檢測靜電引起的mos器件潛在損傷以及注入損傷。
  11. The emphasis is about the metal line reliability, contact reliability, gate oxide integrity, and hot carrier injection in test. based on the test datum, the reliability of 1. 0 m process on single failure mechanisms is evaluated, and all the test structures are explained

    測試內容上著重介紹了金屬化完整性測試、氧化層完整性測試、連接完整性測試和注入測試,根據測試數據,對1 . 0 m工藝線單一失效機理的可靠性進行了評價,對不同測試結構的作用進行了說明。
  12. Under hot carrier stress, device degradation is the consequence of hot carrier induced defect generation locally at drain side

    應力條件下,器件的退化主要是由於在漏極附近由產生的損傷缺陷引起的。
  13. In order to investigate the effect of high - field hot - carrier on devices and circuits, the electrical stress experiment is carried out with 1. 2 n m, 1. 0 n m and 0. 8 u m channel length home - made mosfet ' s by the monitor system with ate and cat technology. by using the fresh and degraded experiment data, bsim2 model parameters are extracted

    為了分析研究高場效應對器件和電路特性可靠性的影響,採用自動測試與cad技術相結合的監測系統,對國內溝道長度1 . 2 m 、 1 . 0 m和0 . 8 m的mosfet進行了電應力退化實驗,並根據實驗結果提取了退化前後器件的bsim2模型參數。
  14. Stress - dependent hot carrier degradation for pmosfets structure under stress mode vg

    2應力模式下應力相關的退化
  15. Tddb and hce always take place simultaneously under device operation conditions. hot - carrier enhanced tddb effect of ultra - thin gate oxide is investigated by using substrate hot - carrier injection technique

    在通常的工作條件下,氧化層的經時擊穿和效應總是同時存在的。
  16. Similar to hot carrier degradation, asymmetric on - current recovery was also observed and discussed. device degradation behaviors are compared in low vd - stress and in high vd - stress condition

    在自加退化中我們也發現了類似退化中的非對稱性恢復現象,並對其退化特點和模型進行了討論。
  17. This dissertation investigates the breakdown theory and reliability characterization methods of the time dependent dielectric breakdown ( tddb ) for the ultra - thin gate oxide, and the hot - carrier effect ( hce ) in deep sub - micron mosfet ' s

    本文對超薄柵氧化層經時擊穿( tddb )擊穿機理和可靠性表徵方法以及深亞微米mos器件效應( hce )進行了系統研究。
  18. Finally, according to the mosfet ' s parameter degradation due to hot - carrier effects and different application environment of mos devices on analog and digital circuits, the circuit structures for hot - carrier immunity are proposed for digital applications by adding a schottky diode in series with the drain of the nmosfet suffered heavily from hot - carrier degradation.,

    即在受退化效應較嚴重的n mosfet漏極串聯一肖特基二極體的新型cmos數字電路結構和串聯一工作于線性區的常開n mosfet的mos模擬電路結構。經spice及電路可靠性模擬軟體bert2
  19. This paper also presented the structure of soi bjmosfet and discussed and analyzed the advantages of this device by comparing with the bulk bjmosfet. its advantages are as fellow : no latch - up effect, better capability of resisting invalidation, much smaller parasitic capacitance, weaker hot - carrier effect and short - channel effects, and simpler technics, and so on

    通過與體硅bjmosfet比較,討論和分析了soibjmosfet的優點:無閂鎖效應、抗軟失效能力強、寄生電容大大降低、效應減弱、減弱了短溝道效應、工藝簡單等。
  20. And for analog applications by adding a normally - on nmosfet in series with the n - mosfet in an analog circuit respectively. according to spice3f5 and bert2. 0 simulation results, the substrate current of new structure cmos inverter is suppressed to about 50 % of its original value and good hot - carriers resistant behaviors are obtained without adding any extra delay

    0對倒相器的模擬結果表明:新型cmos數字電路結構結構使襯底電流降低約50 ,器件的退化效應明顯改善而不會增加電路延遲;巳該電路結構中肖特叢一級管可在nmosfet漏極亙接製作肖特基金半接觸來方便地實現,工藝簡單又無須增加晶元而積。
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