狀態寄存器 的英文怎麼說

中文拼音 [zhuàngtàijìcúnqì]
狀態寄存器 英文
bit status register
  • 狀 : Ⅰ名詞1 （形狀） form; shape 2 （情況） state; condition; situation; circumstances 3 （陳述事件或...
  • 態 : 名詞1. （形狀; 狀態） form; condition; appearance 2. [物理學] （物質結構的狀態或階段） state 3. [語言學] （一種語法范疇） voice
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 狀態 : status; state; condition; state of affairs: （病的）危險狀態 critical condition; 戰爭狀態 state o...
  1. The floating - point status and control register fpscr captures status and exceptions resulting from floating - point operations, and the fpscr also provides control bits for enabling specific exception types, as well as for selecting one of the four rounding modes

    浮點狀態和控制寄存器（ fpscr ）捕獲浮點操作的狀態和異常結果， fpscr還具有控制位，以支持特定的異常類型和對四種舍入模式之一的選擇。
  2. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    搭建了一個驗證系統，通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  3. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  4. To put one or more storage locations or registers into a prescribed state, usually that denoting zero

    將一個或多個存儲單元或者寄存器置成預先規定的狀態，通常置成零狀態。
  5. The complete state of a computer, memory contents registers, flags, etc. at a selected instant of time

    在選定瞬時計算機、內存內容、寄存器、標志等的完整狀態。
  6. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  7. The state of all registers, memory locations and other operative conditions

    所有寄存器、存儲單元和其它運算條件的狀態。
  8. Csr information technology - microprocessor systems - control and status registers architecture for microcomputer buses

    信息技術.微處理機系統.微機總線用控制與狀態寄存器
  9. The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  10. Bit status register

    位狀態寄存器
  11. A method of inte * * cing with hardware that involves repeatedly reading a status register until the device has reached the awaited state

    一種硬體交互方法，不斷讀狀態寄存器，直到設備進入等待狀態。
  12. A method of interfacing with hardware that involves repeatedly reading a status register until the device has reached the awaited state

    一種硬體交互方法，不斷讀狀態寄存器，直到設備進入等待狀態。
  13. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼，以及多時鐘同步的控制流設計方法；進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
  14. An important first step in system debug which checks out in a single step mode the simplest instructions that enable information to is entered into registers and which permit system states to is set up

    系統調試中重要的第一步，用單步方式檢查出可使信息送入寄存器的最簡單的指令以及那些允許建立系統狀態的指令。
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