硬體指令 的英文怎麼說

中文拼音 [yìngtǐzhǐlìng]
硬體指令 英文
hardware instruction
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 指 : 指構詞成分。
  • 硬體 : hardware
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  1. The codewarrior instruction set simulator provides a quick and easy way to begin developing code without the requirement for access to hardware

    指令組模擬器提供開始開發代碼的快速簡便的方式，無需接入硬體。
  2. Supervise the implementation of detailed network optimization, such as : network performance indicators analyzing, signaling trace, parameters and handover relationship checking, sites and hardware detecting, radio signal coverage and interference problems solving etc, in order to improve the whole network service quality

    負責具體優化措施實施，如進行話務指標分析，信令跟蹤，參數及切換關系檢查，站點及硬體故障檢查，信號覆蓋及干擾問題檢查等等，以提升整體網路服務質量
  3. The designed model is compiled into custom instruction of nios processor via sopc interface, and made up hardware accelerator interface model

    最後將該模塊通過sopc介面編輯成nios處理器的用戶指令，組成硬體加速器介面模塊。
  4. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  5. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  6. An emulator is a software or hardware approach to emulate a hardware platform on other platform. jit ( just - in - time ) compiler is widely adapted to speed - up emulation, which compiles the instruction of the source platform into target instruction on - the - fly

    由於硬體平臺的不同，一個高效的模擬器可以採用即時編譯器（ just - in - timecompiler ）技術，即時的把源機器指令編譯成目標機器指令運行。
  7. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  8. This software system of chip simulation ' s main function is simulate the main logic circue chips, 8088cpu, memory, registers, data _ bus, address _ bus, control _ bus and other chips. this function is based on the object - oriented technology, construct the chip object by the chip classes that we defined. because this system need to simulate the detail function of computer hardware, so this system simulate the 8088cpu ' s order system, support the basic compile languages. one of the feture of this system is the simulation of a static memory, the room of the memory can be configured by testers from 1k to 64k

    由於本系統在模擬過程中需要完全模擬計算機硬體的工作原理，因此本系統還模擬了8088cpu的基本指令系統，支持基本的匯編指令，在實驗過程中可以由實驗者輸入相應的匯編指令以執行操作，並查看各晶元器件的引腳參數變化情況。本系統模擬的一個特點是動態模擬了存儲器的大小，存儲器容量可以由實驗者根據需要自己設置，范圍從1k到64k 。
  9. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  10. An abnormal condition detected by the hardware. examples are : attempts to execute a privileged instruction and arithmetic traps such as overflow, underflow, and divide by zero

    一種由硬體檢測到的非正常狀態。例如:企圖執行一條特權指令和諸如上溢出、下溢出與除0等的算術運算陷井。
  11. Plc, robot and cad / cam are called the three major pillars in the modem factory automation. plc, as the head of the three, has become the leading basic automatic equipment in the field of the industry control in the early 1980s " but as a matter of fact, plc being with the lack of friendly man machine interface, rnakes no close relationship between human and machineometimes it even can not be promoted and applied in some fields aiming at the situation mat those imported products are too expensive while domestic products are of rare famous brands, a plc man - machine interface - plc monitor is developedthis paper systemically introduces the developing procedure for the whole system, including how to design hardware and software system. especially emphasizing plc communication protocol. real time message accessing, lcd controller instruction set, definition of data construction for message & tag screens and how to display thern, assignment of internal resource of cpuealization in software among plc & manitor, file format defining a nd download of user data, etcplc monitor will compensate some weakpoints of plc, and extend the application rangeimultanneously enhance the performance of plc and increase the attached value of mechanical machines, undoubtedly it will see hight market prospect

    針對人機界面進口產品的高昂價格和國產品牌稀少的這一現狀，研製開發了一種plc人機界面? plc監控器。本文系統地介紹了整個系統的開發過程，包括硬體系統、軟體系統的設計及實現，重點介紹了plc通信協議，監控器的基本工作原理以及期望實現的功能，監控器電源電路、 sram存儲器掉電保護電路、 cpu監控器電路、按鍵輸入電路的設計及按鍵狀態的讀入，時鐘信息的設定與讀取， cpu液晶顯示器指令系統，信息畫面及標簽數據結構的定義及顯示方法， cpu內部資源的分配，監控器與plc通信的軟體實現，文件格式的定義以及畫面數據的下載等。 plc監控器彌補了plc一些方面的不足，可以擴大plc的應用范圍，提升機械設備的檔次，增加設備的附加價值，具有一定的市場前景。
  12. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  13. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  14. The fixed - point dsp program is given which are based on the analysis in the feather of the video signal and the 16 - bit fixed - point dsp - - tms320c5402. at last, the result and quantity of calculation are analyzed to prove that the speed and precision of calculation are matched to the system requirement

    在深入分析了線性調頻脈沖壓縮信號產生過程和特性的基礎上，結合16位定點dsp ? ? tms320c5402的硬體結構和指令系統的特點，編寫了定點dsp程序，並對程序的計算量和計算結果進行了分析，表明演算法的速度和精度都可以滿足系統的要求。
  15. This paper mainly focuses on the following three field : system structure, system hw / sw ( hardware / software ) partition. synthesis and verification. and presents a hw / sw co - design method based on ip ( intellectual property ) core. we use this method to design asip, and verify this virtual machine using instruction codes, ac - 3 codes and ts ( transport stream ) flow

    本文從晶元系統的整體入手，重點從系統的結構、軟硬體分割以及晶元系統的設計驗證三個方面對該晶元系統的設計做了深入的研究，提出了一種基於ip核的軟硬體協同設計方法，運用該方法對asip進行設計，並採用虛擬機的模型，採用指令集程序、 ac - 3解碼程序、 ts流程序進行模擬驗證。
  16. The chapter one of the thesis introduces the development status of the present digital program exchange system and the main task of devising a new console ; chapter two gives the relevant theories about channel encoding ; chapter three simply introduces digital program exchange system named nd120 ; chapter four presents how to find out relevant data ; chapter five and six describe in detail the hardware structure and software structure of the new console respectively ; chapter seven demonstrates in detail the new interface of this console

    論文第一章介紹了數字程式控制調度交換系統的發展現狀和設計新型調度平臺需做的主要任務;第二章詳細介紹了調度平臺的總體設計及相關的通道編碼理論;第三章簡要介紹了nd120數字程式控制調度交換系統;第四章描述了調度指令的提取過程;第五章和第六章分別介紹了新型調度平臺的硬體結構和軟體結構;第七章則詳細描述了調度平臺介面的設計過程，這也是本文的主要創新點。
  17. Makes an investigation of interpretive principles and key techniques of plc ladder diagram language based on fx2n series plc instruction set, and proposes interpretive methods of basic program instructions, sfc instructions and application instructions on cygnal f040 single chip system, as well as the design and debugging of hardware and software. 3. analyzes the can controller of cygnal f040

    （ 2 ）針對fx2n系列plc指令集，對plc梯形圖語言的解釋原理和關鍵技術進行了詳細的研究，提出了在cygnalf040單片機硬體系統上實現plc基本邏輯指令， sfc指令和功能指令的解釋方法，完成了其硬體和軟體的設計和調試。
  18. We take some measures to prevent the emergence of disturbance when we design the hardware. for example, we increase the copper breadth according to the magnitude of the electric current. the rc circuit is used to absorb the spark generated by buttons and relays when they are putted at the same time, we use the redundancies instruction technology and the trap technology in software aspect avoiding the interference, which can assure the system work credibility

    在硬體上，我們設計印刷電路板時採取一些措施如根據電流的大小，將相對應的銅線寬度加粗，利用rc電路加以吸收按鈕、繼電器等零部件操作時產生的火花等防止干擾的產生；在軟體上，我們採用了指令冗餘技術和軟體陷阱等抗干擾措施，以保證系統可靠工作。
  19. 4. the dsp ' s structure, characteristic, abundant hardware resources and efficient code are introduced in detail ; the control elementary diagram and system frame are given, designed the hardware circuit diagram, make out the program

    Dsp控制軟、硬體的實現及模擬詳細介紹dsp晶元的特點、結構、豐富的片內資源、高效的指令代碼，並根據前述的控制模型，給出了控制原理圖、系統框圖，設計了控制電路，編制了控制軟體。
  20. The emulator has to intercept most of the instructions used for guest - kernel - to - application communications and has to model a complete set of virtual hardware devices

    模擬器不得不為guest - kernel - to - application通信攔截大部分指令，也不得不模擬一組完整的虛擬硬體設備。
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