碼元同步 的英文怎麼說

中文拼音 [mǎyuántóngbù]
碼元同步 英文
code element synchronization
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 步 : Ⅰ名詞1 （步度; 腳步） pace; step 2 （階段） stage; step 3 （地步; 境地） condition; situation; st...
  1. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式（ 16qam和4 - qpsk ）進行了模擬工作並給出了模擬結果，同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試；然後在基於軟體無線電思想的數字處理平臺（該數字處理平臺實現了中頻數字化）上用dsp軟體完成了載波的相位跟蹤。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. The function of video frequency gathering board is to reveal the compound television signal from the computer to carry on a / d transforms, rgb separation processing and so on, output 24bits rgb signals and the synchronized signals. these functions were finished by video frequency decoding chip saa7111 made by philip corporation

    視頻採集板的功能是利用philip公司的視頻解碼晶元saa7111 ，對計算機顯卡輸出的復合電視信號進行a / d轉換， rgb分離等處理，輸出24位rgb信號和同步信號。
  4. The method of picking up synchronizated signal is digital phase - locked loop, which is picking up phase information from the suddenly toggle between codes

    提取碼同步信號一般採用鎖相環技術，利用碼元間存在的瞬間跳變獲取需要的相位信息。
  5. The goal of this thesis is to accomplish base - band channel coding / decoding, fh framing / de - framing and fh synchronization, and also to control the modulator and demodulator in the prototype system. all these functions are implemented with a tms320vc5409 dsp

    作為項目的一個重要組成部分，本文採用dsptms320vc5409實現了基帶處理部分的通道編解碼、跳頻意義的組拆幀和跳頻同步、並對調制解調晶元讀寫寄存器進行了配置。
  6. Survey on timing recovery method in digital receivers

    接收機碼元同步演算法的研究
  7. An improved algorithm for symbol synchronization and symbol decision are proposed. their performance at different level of snr and frequency offset are discussed by simulations

    本文提出了一種改進的碼元同步演算法和改進的碼元判決演算法，通過模擬分析了它們的抗噪聲和抗頻偏性能。
  8. Secondly, a dstft ( discrete short time fourier transform ) - based demodulation method for the 2fsk signal is studied and algorithms for symbol synchronization and symbol decision are analysed

    重點研究了基於離散短時傅里葉變換解調2fsk信號的方法，分析了幾種碼元同步演算法和碼元判決演算法。
  9. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  10. The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed

    在此基礎上設計了基於scc準同步的一種時鐘恢復實現電路和兩種字元型起止式同步電路（實現了一種） 。設計了正碼速調整技術中快慢時鐘的三種控制電路。
  11. At last, this paper analyses the delay correlation properties of 2fsk signal, and proposes a new algorithm for symbol synchronization, which shows better performance when frequency offset exists

    最後，從抗頻偏的角度出發，通過分析2fsk信號的延遲相關特性，給出了一種碼元同步演算法，具有良好的抗頻偏性能。
  12. The controller adopts tms320f240 dsp as its main control unit, using code wheel for angle measurement, using synchronous serial communications interface for the duplexing data communication between the controller and the upper computer, using rs - 232 interface for the communication between the pitch axis controller and the azimuth axis controller, and then developed the interface circuit to the motor driver

    根據控制器研製要求，提出總體方案。控制器採用dsp作為主控單元，利用光電碼盤測角，利用同步串列通信介面與上位機進行雙向數據通信，利用rs - 232介面進行俯仰軸和方位軸控制器之間的通信，並研製了與電機驅動器的介面電路。
  13. The data - sampling section completes analogue - to - digital conversion using fpga and high speed adc, then transmits these data to processing communication equipment in some format. because fpga has high speed processing capacity, this section can obtain very high sampling rate

    數據採集部分採用現場可編程門陣列（ fpga ）作為與模數轉換器件（ adc ）的介面，在單晶元內實現了同步采樣控制、數據編碼傳輸的功能。
  14. In the part of platform designing, proper peripheral chips are chosen according to the audio signal format. and how to achieve channel synchronization in the receiving part is an important aspect of wireless transmission system. in order to solve this problem, three algorithms are used ; those are scramble / descramble, improved over - sampling, and frame synchronization protocol

    在硬體驗證平臺的設計部分，文章根據音頻信號的特點選擇了適當的外圍晶元，並且針對無線傳輸接收端的同步問題，採用了三種演算法來減少失步現象，即擾碼/解擾演算法，改進型的過采樣演算法，以及幀同步協議。
  15. In this thesis, the principle of polarized light wave transmit in optical fiber is researched, i. e. principle of ternary optical fiber communication is researched. based on the researches, the construction of ternary codes optical end machine and 3b2t optical end machine used in two - state fiber net are designed. the construction and component of circuits in 3b2t optical ( called sign converter circuit - scc ) are designed particularly, including : the clock synchronization module, the data synchronizing, code converting module, frame managing module and error exam and managing module

    本文研究了線偏光波動理論以及在光纖中的傳輸原理，研究了三值光通信系統原理和器件原理；在此基礎上，設計了三值光端機和在現有兩值光纖網中實現三值光通信的3b2t三值光端機的組成結構，詳細設計了3b2t三值光端機的電路組成部分（稱為電信號變換電路scc ） ，包括：時鐘同步模塊、數據同步模塊、碼元變換模塊、幀處理模塊及差錯檢測和處理模塊；而且在三值光纖通信基礎上，提出了四值光通信的原理和偏分復用的實用化方法。
  16. Code reviews - creating unit and component tests, as well as detecting memory and performance bottlenecks, in parallel to writing code - returns in form of higher quality code and reduced development time

    透過建立自動程式碼審查- -與程式碼編寫同步進行，來建立單元和元件測試，並發現記憶體和效能瓶頸- -帶來了高品質的程式碼，同時也減少了開發的時間。
  17. Take the hoc based blind modulation detection algorithm as an example, the relationship between the blind modulation detection algorithm and synchronization is investigated. an unproved detection algorithm robust to frequency offset is proposed which solves the problem caused by the error in carrier synchronization. how to synchronize a received signal with unknown modulation type is studied and a blind algorithm to estimate symbol timing of the signals with unknown modulation type is presented

    研究了載波同步和碼元定時同步與調制方式盲檢測演算法的關系；以自適應單載波中高階累積量調制方式盲檢測演算法為例，對于載波同步誤差引起的頻偏問題，提出一種基於頻偏穩健的mdpsk信號調制方式盲檢測演算法；對于未知調制方式信號的定時同步問題，提出一種盲定時估計演算法，該演算法可以估計mdpsk和mqam信號的定時同步信息，實現數字信號的同步分類；提出了一種基於調制方式盲檢測的自適應接收機結構，把調制方式盲檢測，信噪比估計和同步解調聯合起來進行，實現調制方式隨通道質量而自適應變化的信號的正確接收。
  18. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
  19. Angles decrypted and software compensated with dsp and cpld, the angular displacement of the rotating set of axes with high resolution and precision can be obtained by taking the circular inductive synchronizer as the angle meter

    摘要用圓感應同步器作為測角元件，採取dsp和cpld進行角度解碼和軟體補償，可以得到極高解析度和測量精度的旋轉軸系的角位移數字量。
  20. A sequence of binary characters recorded at the beginning of each block on a phase - encoded magnetic tape for the purpose of synchronization

    相位編碼磁帶上，記錄在每個數據塊的開始處、供同步用的二進制字元序列。
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