連線延遲 的英文怎麼說
中文拼音 [liánxiànyánchí]
連線延遲
英文
wiring delay-
The brain can institute its own connections on the central processing of events such that, at the microtemporal level, it manages to “ antedate ” some events so that delayed processes can appear less delayed and differently delayed processes can appear to have similar delays
大腦在處理發生在大腦中樞的事件時，會制定自己的連線，結果是，大腦會讓某些事件的感知早個幾毫秒，所以延遲的過程，看起來就比較沒那麼延遲，而且不同延遲的處理過程，看起來也像是有著相同的延遲。The other is train communication network. based on the protocol of " iec 61375 - 1 ", published by iec in 1999, the data to be transmitted is classified into urgent periodic variables and deferrable random messages. in this paper the whole net is decomposed into two layers : train bus and vehicle bus
文中參考iec組織1999年公布的「 iec61375 - 1 」標準協議，將整個列車網路分為連接各個車廂主機的上層列車總線網和連接單個車廂內負責控制、檢測等子設備的下層車廂總線網，同時將傳輸的數據類型區分為實時的周期性過程數據和可延遲的偶發性消息數據。Interconnect wire delay questions in deep submicron ic design
深亞微米集成電路設計中的互連線延遲問題Interconnection dimensions become the limitation for new performance design while the size traditional transistor has met the demand of challenge. thus, the study of interconnection delay becomes more important for current circuit design and technology
為了提高ulsi的頻率特性，按比例縮小晶體管的特徵尺寸的努力受到了互連線本徵特性和寄生效應的限制，互連線的rc延遲成為ulsi進一步提高頻率特性的瓶頸。Wireless wide - area networks ( wwans ) are charactered by very low and variable bandwidths, very high and variable delays, significant non - congestion related loss, asymmetric uplink and downlink channels, and occasional blackouts. additionally, the majority of the latency in a wwan connection is incurred over the wireless link
無線廣域網（ wwans ）由於以下特徵而有別于有線廣域網（如internet ） ：較低並且易變的帶寬，很高且易變的延遲，與擁塞無關的數據丟失，非對稱的上行和下行通道，以及偶爾的昏眠狀態，此外，在無線廣域網上的大部分的延遲發生在無線連接部分。Due to restriction with the array aperture transition time, traditional phased array radar works under relative narrow signal bandwidth, so this restricts the application of phased array radar in the field where high performance is demanded. however, optically controlled phased array radar ( ocpar ) adopts the photoelectron technology, counteracts the aperture transition time via the method of optical true time delay ( ottd ), so it can realize wide instantaneous bandwidth and squint - free operation ; meanwhile, it can realize the miniaturization of phased array radar and has super anti - electromagnetism interference capability
而光控相控陣雷達採用光電子技術，通過光實時延遲的方法來抵消孔徑渡越時間，可以實現相控陣雷達的寬帶寬角掃描;同時也可以使得相控陣雷達小型化，並具有強的抗電磁干擾的能力;另外，由於光纖傳輸具有損耗低、頻帶寬等固有優點，採用光纖連接雷達天線和雷達控制中心，可以使兩者的距離較採用同軸電纜有較大的提高，更有利於保護雷達控制中心。This update fixes false error messages that occur when the latency of internet connections causes problems while adding time
網際網路連線延遲導致誤時問題時將顯示的false錯誤訊息，此更新可修正這個錯誤訊息。When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束When feature size comes to 0. 35 m, interconnect delay has contributed 70 % to total delay. distribution of delay parameters lies on actual implementation of layout, which results in the fact that timing closure has become the chief problem. so synthesis technology must be based on timing to insure timing closure
特徵尺寸進入0 . 35 m后，互連線延遲佔到系統延遲的70以上，而延遲參數的分佈又取決于版圖的具體實現，導致時序收斂成為設計的首要問題，因此綜合技術必須要基於時序，保證時序收斂。As shopping - mall - style chips continue to sprawl outward, for example, it becomes increasingly hard to keep the photolithographic image in focus at the edges
而且連接到遠處的導線太長，會導致訊號延遲，因而減低了晶片的效能及復雜的功能。At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2
在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。For a class of continuous - time switched linear systems with state delay, the problem of designing asymptotically stabilizing state feedback controllers and output feedback controllers is investigated
摘要針對一類具有狀態延遲的連續線性切換系統，研究了其漸近穩定性及狀態反饋和輸出反饋鎮定控制律的設計問題。分享友人