邏輯前端程序 的英文怎麼說

中文拼音 [luóqiánduānchéngxù]
邏輯前端程序 英文
logical front end
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 前 : Ⅰ名詞1 （在正面的） front 2 （次序在先的） first; top 3 （過去的; 較早的） ago; before; preceding...
  • 端 : Ⅰ名詞1 （東西的頭） end; extremity 2 （事情的開頭） beginning 3 （門類; 方面） item; point 4 （原...
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 邏輯 : logic
  • 程序 : 1 （進行次序） order; procedure; course; sequence; schedule; ground rule; routing process 2 [自動...
  1. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  2. Besides the logic design, we also divide our system into two parts - background database and forward user ' s interface, and detail the technology design of the two parts respectively

    除了對系統經行了邏輯設計，在技術上我們將系統分為后臺的數據庫與前端用戶程序兩大部分分別經行了詳細的論述。
  3. It s a good practice to code an application from " back to front " - with the " back " of an application being its data access and working areas, moving to the programmatic logic, and finally the user interface areas

    「從後向前」編寫應用程序是一個很好的實踐- -其中應用程序的「後端」指的是數據訪問和工作區，然後轉移到程序邏輯，最後是用戶介面區。
  4. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  5. There is less of a load on the server than with a web front end, because the server does not have to perform all of the application logic

    服務器上的負載比web前端的負載少，這是因為服務器不必執行所有的應用程序邏輯。
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