邏輯與電路 的英文怎麼說

中文拼音 [luóyǔdiànlù]
邏輯與電路 英文
logical and circuit
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The method of connecting timing into 1ogic i s explained in waveform po1ynomia1 on the basis of waveform concept in boo1ean process theory. and an ana1ytica1 de1ay mode1 that is close to practice circuits is found

    並在布爾過程論中定義波形的基礎上，說明了邏輯與時序在波形多項式中的結合方法，建立了接近實際電路的解析延遲模型。
  2. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  3. It integrates the functions of servo amplifier, dynamic operator, position transmitter and remote communication. many new functions have added to its original ones, such as the real - time logical judgment, malfunctions self - diagnosis, alarm & protection, led display, on - line setting and adjustment of functional parameter and position transmitter, power - absence data auto - protection, watchdog system protection, and the long - range communication with pc

    系統集伺服放大器、電動操作器、位置發送器及遠程網路式通信功能於一體，在保留對應部分原有功能的同時，還新增了邏輯實時判斷、故障實時監控、 led動態顯示數據、功能參數設置、掉電數據自保護、 「看門狗」電路保護、位置發送器在線調節、與遠程工控機數據通信等眾多功能。
  4. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  5. In this paper, based on the study of vga graphic displaying theory and the theory of synchronizing display between led large - screen display system and crt image, a method, bit plane addressing method which has good effect -. high ratio of performance to price and can be implemented easily in circuits is discussed. and the principle and the implementation of the multi - gray led display system with programmable logic devices cpld and fpga are analyzed in detail

    本文在分析vga圖象顯示原理和led大屏幕與crt視頻圖像同步顯示原理的基礎上，論述了一種顯示效果較好、性能價格比高、電路上易於實現的方法? ?位平面尋址法實現多灰度圖象，並詳細分析了應用復雜可編程邏輯器件cpld和在線可編程邏輯器件fpga實現多灰度彩色led大屏幕圖像顯示的原理及電路實現。
  6. We adopt asic design technique, using advanced eda tools to design and simulate ccu

    Ccu採用asic的全定製電路設計方法，使用先進的eda設計工具進行邏輯設計與功能模擬。
  7. In chapter three, the all sub - circuits including uvlo, current bias, ldo, oscillator, green mode, slop compensation, power limiting, pwm, ovp, blanking time generator, logic controller are designed and simulated. as a result, all of the sub - circuits are satisfied the requirements

    本文第三章對集成電路內各個模塊包括欠壓保護、電流偏置、 ldo 、振蕩器、綠色模式、斜坡補償、功率限制、脈寬調制、過壓保護、前沿消隱、邏輯控制電路等進行了設計與模擬，且達到了預定的設計目標。
  8. The fault diagnosis system includes four parts : sampling and insulation of the synchronous signal, sampling of the voltage waveform of the rectifier, logic pre - processing and dft analysis, display and alarm circuit

    故障診斷系統主要包括同步信號的取樣與隔離、整流電壓的采樣、邏輯預處理及dft分析，診斷顯示報警電路等四部分。
  9. Therefore, it can be named by “ the specific demultiplexer of sdh ”. the design of pos line card was discussed and we also have finished the control logic of the hardware platform of the specific demultiplexer

    論文主要討論專用分接器的pos線卡設計和硬體平臺的控制邏輯電路設計與實現。論文首先對基於fpga的10gbps的pos線卡的設計方案進行了研究。
  10. The ina128 is used by left leg ' s driver circle and the aims are to enhance the cmrr and reduce the disturbance of 50hz. the part of a / d transmitting chip is the adc0809 which have a eight - channel transmitter, a eight - bit a / d transmitter and the logical control by microprocessor

    考慮到家庭監護的實際應用，精度的要求不是很高， a / d轉換器採用的是adc0809 ，它有8通道多路轉換器、 8位模/數轉換器和與微處理器兼容的控制邏輯電路。
  11. It is easier for us to realize the hardwave circuit, and the content of sine wave at least by 45db is the projecting advantages

    本文主要論述一種實用的時序邏輯電路的設計與實現設計一個十字路口交通燈自動循環亮滅的控制器。
  12. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。
  13. In this way, a simple and direct relation was build up between logical transitions and dynamic current, which makes possible iddt testing pattern generation on logical level

    該方法在電路邏輯跳變與電路動態電流之間建立了一種簡單直觀的關系，使得動態電流測試產生能夠在邏輯級上得以實現。
  14. By exploring the characters of dynamic power supply currents of digital circuits using spice, this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another

    本文通過spice實驗研究數字電路動態電流的特性，分析了數字電路的動態電流與電路邏輯狀態轉變之間的關系。
  15. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  16. Based on many other circuit formats, a new kind of logic - level circuit representation, called unified middle - level circuit format ( umcf ), is defined in this paper, in which some special operations on circuit related with power estimation and low power design. umcf can not only interchange circuits of different formats, but also convert circuits to hspice acceptable files, which can be used for transistor level power estimation

    本文結合多種不同的電路格式，自主定義了一種邏輯級電路的中間表示形式（稱為umcf ）和一系列極具特色的與低功耗技術相關的操作，它不但可以實現與其他多種電路格式之間的相互轉換，還可以將電路直接轉換成hspice可以接受的文件，進行晶體管級的電路功耗估計，這樣可以在公認的高精度的功耗模擬器上，對本文的結果進行有效的驗證。
  17. With the rapid development of semiconductor, digital integrated circuit ( p, memory, standard logic gates, etc. ) and advance computer technology, the various measuring instruments ( virtual instruments ) with the powerful function of pc are produced in different industrial and scientific research fields. as we all known, the traditional instruments are usually built with discrete components and small scale ics, the disadvantages are obvious in system design, debugging and maintenance

    隨著半導體技術與數字集成電路（微處理器、存貯器以及標準邏輯門電路等）技術的迅速發展，特別是隨著計算機技術的發展，在工業生產和科學技術研究的各行各業中，人們利用pc機的強大處理功能代替傳統儀器的某些部件，開發出各種測量儀器（虛擬儀器） ，傳統儀器的數字邏輯部分多是採用分立集成電路（ ic ）組成，分立ic愈多，給系統的電路設計、調試及維護帶來諸多不便。
  18. We design inversion control circuit with cmos figure pll cd4046 act as core and microprocessor 80c196kc act as assistant controller. adopting a control method that combine fuzzy controller and pll control, improve induction heating power succeed in startup. adopting electric current voltage pair closed loop feedback design, with trough route capacitance voltage and trough route electric current act as pair closed loop feedback signal, guarantee induction heating power output accuracy

    並對系統主電路的元器件參數進行了詳細的計算；設計了以cmos數字鎖相環cd4046為核心、以80c196kc作為輔助控制器的逆變控制電路；採用了模糊邏輯與鎖相環相結合的控制技術，提高了電源的啟動成功率；採用電流、電壓雙閉環反饋方案，採用槽路電容電壓和槽路電流作為反饋信號，從而保證了電源功率的輸出精度。
  19. Prospect teli - monitering system for elevator is prospect s new product. it has confirmed by experts on elevator as high technology products. through photo - electric isolation part, it connects the control circuit and sensors on elevator to collect, analyse the real - time status data

    該產品通過光電隔離與電路控制系統及傳感器連接，由電梯故障信息採集分析儀實時採集電梯的運行狀態和有關數據，並對採集到的電梯信號進行邏輯判斷，發現故障，將相關數據傳輸中繼器。
  20. Designer can synthesize the pci core and the user ' s logic into an fpga chip, and can do simulation analysis to test the pci core and the user ' s logic. this technique can increase the design and debugging time, develop the capability of the system

    設計者可以將pci用戶邏輯與pcicore集成在一片fpga里，並且可以在頂層通過模擬來驗證pci介面以及用戶邏輯設計的正確與否，這樣可以大幅度提高調試速度，縮短開發周期，提高電路板的集成度和系統的性能。
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