高摻雜層 的英文怎麼說

中文拼音 [gāochānzácéng]
高摻雜層 英文
heavily doped layer
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 摻 : 摻動詞[書面語] （持; 握） hold
  • 雜 : Ⅰ形容詞（多種多樣的; 混雜的） miscellaneous; varied; sundry; mixed Ⅱ動詞（混合在一起; 攙雜） mix; blend; mingle
  • 層 : i 量詞1 （用於重疊、積累的東西 如樓層、階層、地層） storey; tier; stratum 2 （用於可以分項分步的...
  • 摻雜 : 1. mix; mingle2. doping; inclusion; addition; adulteration
  1. In this dissertation, refining grains, depositing conductibility carbon film on the surface of the particles and doping mg ~ ( 2 + ) into the lattice of lifepo4 were adopted to improve the electro - chemical performance of the cathode material. the cathode material lifepo4 mainly has two flaws, the low conductibility and the slow li + ion diffusion, which have a bad influence on the performance of the cathode material

    論文主要針對制約正極材料lifepo _ 4性能的兩大致命的缺點，即低的電子導電率和低的鋰離子擴散速率，採取材料顆粒的細化、顆粒表面沉積碳導電層以及mg ~ （ ~ （ 2 + ） ）離子摻雜等措施對其進行改性探索，以提高正極材料lifepo _ 4的電化學性能。
  2. The reason to cause this phenomenon is due to the change of electric field in the blue oled to induce the probality of the carrier shifted and the hole - electron recombination zone changed, which was a possible alternative to achieve color display. 3 ) device with the structure of ito / npb / adn : balq3 / alq3 / mg : ag was fabricated. when the balq3 dopant concentration was about 25 mol %, a high performance devcie with luminous efficiency of 1. 0 lm / w, the peak of emission spectrum at 440 nm, the cie coordinate at ( 0. 18, 0. 15 ), and half lifetime of unencapsulated device about 950 hrs was achieved

    導致本現象的原因是由於各有機層電場強度的變化影響了空穴和電子的隧穿幾率，從而導致載流子的復合區域發生改變而發出不同顏色的光; 3 ）制備了結構為ito / npb / adn : balq3 / alq3 / mg : ag的藍光oled ，空穴阻擋材料balq3的摻入顯著影響了oled的光電性能，當balq3的摻雜濃度為25mol %時， oled的發光效率為1 . 0lm / w ，發光光譜的峰值為440nm ，色純度為（ 0 . 18 ， 0 . 15 ） ，未封裝器件的半衰期達到了950小時; 4 ）在藍光材料adn中摻雜npb 、 balq3和tbp三種材料時，不僅改善了器件的發光亮度和色純度，而且提高了器件的發光效率和壽命。
  3. During the high - voltage device design, the thick epitaxial layer ldmos which is compatible with current technology was researched. this device used piecewise vld and multiple region structure f reduce field layer. the using of the f reduce field layer effectively reduce the surface electric field of the device, shorten the length of its drift region, enlarge the choice of range of the ion implant dose of the p layer, and effectively restrain the disadvantageously affection on the breakdown voltage of the interface charge qss

    在高壓器件研究中對與現有工藝相兼容厚外延ldmos進行研究，該結構採用分段變摻雜多區p ~ -降場層，有效降低器件的表面電場，縮短器件的漂移區長度，增大p ~ -降場層注入劑量的選擇范圍，並有效地抑制界面電荷qss對器件耐壓的不利影響。
  4. It also put forward that how to select appropriate epilayer doping concentration and thickness, pn junction depth and jte technology to increase the breakdown voltage of 4h - sic mps. a power dissipation model of 4h - sic mps was established

    通過對4h - sicmps擊穿特性的二維模擬，提出如何選擇合適的pn結深度、外延層摻雜濃度和厚度以及如何運用jte終端技術來提高擊穿電壓。
  5. Since polymer light - emitting diodes ( pleds ) were invented, much efforts have been made to improve the brightness and efficiency of its electroluminescence for realizing pled commercial application. we investigated several factors influencing the brightness, efficiency and spectrum characteristics of pleds el, especially focused our attention on the processes of carrier injection, transport, recombination and annihilation factors influencing brightness efficiency of organic electroluminescence ( oel ) in doped single and double - layer pleds

    本文以提高聚合物器件的效率和亮度為目標，提出了提高及b幾種方案，研究了材料性質，器件結構，它們的穩態及瞬態特性及發光機理，特別關注了以兼具電子空穴傳輸能力的分子及摻雜聚合物作成的單雙層摻雜聚合物發光器件中的載流子注入、遷移、復合及湮滅等。
  6. With the development of doping technology, the formation of the base region in high - voltage transistor can be made by b diffusion technology, b - a1 paste - layer diffusion technology, close - tube ga - diffusion technology and open - tube gallium - diffusion technology

    隨著摻雜工藝的不斷發展，高反壓晶體管基區的形成經歷了擴硼工藝、硼鋁塗層擴散工藝、閉管擴鎵工藝到開管擴鎵工藝的發展。
  7. According to the thickness of the soi film, high voltage ic based on soi material ( soi - hvic ) can be divided into thin - film and thick - film. for thin - film soi - hvic, linear drift region doping profile is adopted to satisfy a certain breakdown - voltage, but this process is too complex and its self - heating effect is obvious ; for thick - film soi - hvic, it can take advantage of cmos technology on silicon to obtain the high voltage

    Soi高壓集成電路根據頂層硅厚度可分為厚膜和薄膜兩大類。為了滿足一定的擊穿電壓，薄膜soi高壓電路一般採用漂移區線性摻雜技術，但其工藝復雜，且自熱效應嚴重;而厚膜soi高壓集成電路可以通過移植體硅cmos技術來實現高壓，但是由於其硅膜較厚，介質隔離成為厚膜soi高壓集成電路的關鍵技術。
  8. By the use of iteration method to solve schrodinger - poisson equations when algan barrier layer doped about 1 1018cm - 3, the max sheet density of 2deg is 1 1012cm - 2 and the thickness of 2deg is increasing from 15nm to 40nm with barrier ’ s thickness increasing

    採用迭代法求解schrodinger - poisson方程，當algan勢壘層摻雜濃度為1 1018cm - 3時，二維電子氣濃度最高可達1 1012cm - 2 ，並且二維電子氣薄層厚度隨著勢壘層厚度的增加從15nm增加到40nm 。
  9. As far as the new technology of selective diffusion, the method of printing is used and the phosphoric paste ( high concentration ) is printed at the electrode - site in silicon. afterwards, a thin layer of phosphoric source ( low concentration ) is sprayed on the surface of the non - electrode - site in silicon

    在選擇性擴散新工藝中，我們採用絲網印刷電極的方法在矽片的電極位置印刷濃度較高的磷漿（摻磷sio _ 2乳膠） ，在非電極區噴塗一層濃度較低的磷源，擴散后形成重摻雜和輕摻雜。
  10. According to our theoretic analysis and the realistic fabricating condition, the boa device with double - heterostructure gaas / gaalas has been proposed to obtain 3db bandwidth greater than 2. 5 ghz, half - wave voltage about 5v, extinction - ration less than - 40db, transmission loss of tm mode greater than 45db and transmission of te mode less than 0. 15db. to obtain higher switching speed, we proposed that traveling - wave electrode is applied to boa device

    我們選擇在sigaas襯底上生長重摻雜層，通過控制其厚度來設計速度匹配的boa光開關行波電極，實現boa光開關的高速和高帶寬，本文結合boa型光開關的特點提出一種行波電極型boa光開關結構，其理論3db調制帶寬大於20ghz 。
  11. Graded doping is adopted in both sides of the junction ( double graded doping ). this results in a strong ( drift ) electric field throughout the whole active layer. this field will accumulate minority carriers effectively and the whole internal quantum efficiency is increased

    漂移場的形成是通過mbe技術，在結的兩側都採用梯度摻雜（即雙梯度摻雜） ，從而在整個有源層都建立起一個強的（漂移）電場，有效地利用載流子在電場作用下的漂移作用收集少數載流子，使得總內量子效率得以提高。
  12. In the new structure, a n + buffer layer is introduced into the bulk silicon substrate with a triple - diffusion process. the new structure has two features : one is the feature of npt - igbt : the thin and lightly - doped p + layer and the high lifetimes of the carriers ; the other is the feature of pt - igbt : n7n + structure which can make the n " region very thin

    新結構用三重擴散的方法在n ~ -單晶片上引入了n ~ +緩沖層，仍然保留了npt - igbt中薄而輕摻雜p層和高載流子壽命的本質優點，同時又具有pt - igbt中n ~ - （ n ~ + ）雙層復合的薄耐壓層（即薄基區）的優點。
  13. Thus it is considered that the technique of dz formation by means of rtp may not be suitable for heavily boron - doping cz silicon. since the higher concentration vacancy could decrease the stress inducing by oxygen precipitates, the size of the oxygen precipitation with higher density was smaller in the hb si samples in comparison with the samples without rtp pre - annealing. moreover, as for the technique to generate dz by rtp in lightly boron - doping samples, it was found that the behavior of oxygen precipitation and dz was determined by the annealed temperature, followed annealing and ambient of rtf as well

    結果顯示，對于普通輕摻矽片能形成明顯的很寬的潔凈區的rtp預處理工藝，應用於重摻硼樣品時沒有潔凈區形成，所以rtp預處理獲得潔凈區的工藝不適用於重摻硼矽片，硼的大量摻雜對氧沉澱促進效果大於高濃度的空位對氧沉澱的洲排浙江大學碩士學位論文李春龍：直拉重摻硼硅單晶中氧沉澱的研究促進效果；大量空位的引入，有利於釋放氧沉澱生長過程的內應力，適當增加重摻硼樣品氧沉澱密度，減少其尺寸，並伴有層錯生成。
  14. In this design, the double graded doping solar cell accumulates the minority carriers with the drift field, which is located at the whole graded space. this means that the accumulation of minority carriers doesn ’ t depend on the above conditions

    採用與眾不同的通過在p區和n區都採用梯度摻雜這樣一個所謂雙梯度摻雜，在整個有源層獲得高達104v / cm的漂移電場。
  15. After structure design aimed to high transconductance, parameters of device structure are modified in detail. the simulation results of soi nmos with strained si channel show great enhancements in drain current, effective mobility ( 74 % ) and transconductance ( 50 % ) beyond conventional bulk si soi nmosfet. the strained - soi nmosfet fabrication process is proposed with lt - si ( low temperature - si ) technology for relaxed sige layer and simox technology for buried oxide

    其次，根據器件參量對閾值電壓和輸出特性的影響，以提高器件的跨導和電流驅動能力為目的設計了strained - soimosfet器件結構，詳細分析柵極類型和柵氧化層厚度、應變硅層厚度、 ge組分、埋氧層深度和厚度以及摻雜濃度的取值，對器件進行優化設計。
  16. When a mutually doped transitional layer is introduced, no matter it is added to the interspace of electron transport layer and hole transport layer or to the interspace of the hole transport layer and hole inject layer, it can reduce the defects of the interface and result in the increase of brightness and the decrease of the operating voltage obviously

    我們在器件中引入了互摻過渡層結構，發現不管在電子傳輸層和空穴傳輸層之間，還是在空穴傳輸層和空穴注入層之間採用這樣的摻雜結構，都能夠有效減少有機層間的界面缺陷態，明顯提高了器件的亮度，降低了器件的工作電壓。
  17. The surface treatment was founded to be effective in reducing the rate of mn dissolution into electrolyte and improving cyclability of spinel. after bulk ni - doped spinel lini0. 1mn1. 9o4 was coated with licoo2, the cyclability of material is better than that of pure s

    電化學性能測試表明， oz型層狀理錳氧化物具有優良的電化學循環性能， co摻雜使其容量提高， zn摻雜則使其容量降低。
  18. Mechanical folding test was applied to analyze the crack behavior of dlc films. the results show that the crack appears due to the mechanical stress and the initiation and propagations of the cracks may be suppressed with higher rf power, bias voltage and gas pressure

    機械彎折試驗結果表明，沉積成膜過程中，應選擇較高的氣壓、基板負偏壓、射頻功率以及適量的n摻雜來制備抗往復彎折的、耐失效性能優越的膜層。
  19. Owing to its optoelectronic and chemical properties, cdte is an ideal absorber material for high - efficiency, low - cost polycrystalline thin film. the thesis has investigated the structure, figure and optoelectronic characteristics of cdte polycrystalline thin films, the performance of doped cdte, and the influence of their deposition and anneal process

    Cdte具有良好的光電學性質和化學性質，因此成為制備高效率、低成本的多晶薄膜太陽電池理想的吸收層材料。本文針對cdte薄膜，研究了其制備工藝、摻雜和后處理條件對薄膜結構、形貌和光電學性質的影響。
  20. Firstly we analyze the requirement of sbd of high frequency for the doping concentration and thickness of the epilayer, for the structure parameter of the device. we design the optimum device parameter based on this. 2

    首先，從理論上分析出高頻肖特基二極體對材料的外延層厚度摻雜濃度的要求，以及其它的器件結構參數要求，以此為依據，設計出最佳的器件參數。
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