高速采樣器 的英文怎麼說

中文拼音 [gāosùcǎiyàngqì]
高速采樣器 英文
high - speed sampler
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 采 : 采名詞（采地） feudal estate
  • 樣 : Ⅰ名詞1. （形狀） appearance; shape 2. （樣品） sample; model; pattern Ⅱ量詞（表示事物的種類） kind; type
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  1. A data acquisition system with the following features is realized : ? transmission rate up to 100kbyte / s over usb ; ? system ' s dynamic range as high as 120 db ; ? multi - kind of trigger mode control ; ? sampling rate as high as 100 ksps ; ? 12 - bit a / d conversion accuracy ; ? 32k bytes on - board data memory ; ? the system, which was made up of large - scale electronic chips, is small, light and portable, and suitable for field use

    本設計最終實現了一個瞬態信號數據採集系統，它具有以下特點： ?採用usb介面進行高速數據傳輸，傳輸速度達100kbyte / s ； ?採用浮點a / d轉換技術，動態范圍達120db ； ?多種采樣觸發控制方式； ?最高采樣率100ksps ； ? 12位采樣精度： ? 32kb數據緩存； ?使用新型大規模電子器件，系統結構緊湊，重量輕，適合野外作業。
  2. High precision ad chip is used for intermediate frequency data sampling and fpga of virtex - series is used for the implementation of intermediate - frequency orthogonal system, which includes the sequencing control design for mult - channel radar system with verilog, the application of ip core of digital filter and fifo, as well as the communication control module with dsp. as the master control part, the software programming for the communication between dsp and fpga is designed. the experimental result with hardware circuit shows the design is valid and practical

    採用高精度的adc晶元完成中頻采樣，通過virtex -系列fpga設計中頻正交系統，主要包括通過verilog語言實現多路雷達中頻接收的時序控制，通過濾波器ip核實現濾波器的設計，以及利用c語言實現dsp的通訊控製程序設計。並給出了fpga在資源和速度上一些優化的方法，調試過程中影響中頻正交接收性能測試的因素。
  3. In the second chapter, we firstly present a circuit of 8 - bit, 80mhz samples / s thermometer - decoded dac with hierarchical symmetrical switching sequences which will compensate gradient error, on the basis of 8 - bit dac, we then present high frequency, high definition 12 - bit, 80mhz samples / s current - steering dac

    第二章：提出了具有梯度誤差補償的高速8位、 80mhz溫度計碼數模轉換器，並在此基礎上進一步提出了高速、高精度12位、 80mhz采樣率電流舵結構數模轉換器。
  4. In this dissertation, we studied the tcra1101plus total station position system, which introduced the principle and characters of the instrument ' s closed loop tracking system. also we explained the cause of prism ' s position error and brought forward mathematic model to correct, moreover, the good results has been drawn form the expenriments. the kinetic survey system have been realized, which the sampling rate attain more than 5hz and the position precision can be less than 2mm on condition that targeted - point moving slowly at the velocity below 2cm / s. having finished the survey system to examine whether the fine - tuning stewart platform in good status, we have finished mensurating the position reference of the fine - tuning stewart platform and the offset of the prism

    在此基礎上研製了多臺儀器在線控制高頻采樣動態跟蹤測量系統，采樣率大於5hz ，在跟蹤小於2cm / s低速運動目標時，測量精度好於2mm ；完成對饋源二次精調系統的檢測，包括對二次精調平臺位置基準的標定和觀測棱鏡偏心差的測定；設計不同動態測量實驗，對全站儀動態跟蹤的誤差來源和特點進行了分析；從實驗角度，對全站儀的測量時滯及其穩定性進行了測試分析，給出了定量的結果；比較了全站儀和計算機的內部時間系統，發現兩者存在較大差異。
  5. On the basis of high speed hybrid filter banks adc system, a kind of downsampler model based on bandpass sampling theorem is presented, and analyzed, proved in time and frequency domain, in addition a downsampler is designed according to the model. a class of high effective hybrid filter banks adc system which bases on the downsampler and radio frequency spectrum is proposed, of which digital signal rate falls m times as fast as the former

    作者提出了一種基於帶通采樣定理的抽取器數學模型，對該數學模型進行了時域、頻域的分析證明后，設計了一種基於該數學模型的抽取器，進而根據無線電射頻信號頻譜的特點，提出了高效混合濾波器組adc系統，其數字信號輸出速率比高速混合濾波器組adc系統降低m - 1倍。
  6. The bottleneck of hybrid filter banks adc system is that it cannot sample directly higher radio frequency signal because of lower analog input bandwidth of its adc. in order to remove it, a kind of downsampler model based on nyquist and bandpass sampling theorem is presented, analyzed and proved in time and frequency domain, in addition a downsampler is designed according to the model. on the basis of hybrid filter banks adc system, a class of high speed hybrid filter banks adc system is proposed

    針對混合濾波器組adc系統因其adc模擬輸入帶寬低而不能對頻率較高的射頻模擬信號進行模/數轉換的瓶頸，作者提出了一種基於nyquist采樣定理和帶通采樣定理的抽取器數學模型，對該數學模型進行了時域、頻域的分析證明后，設計了一種基於該數學模型的sha抽取器，進而在混合濾波器組adc系統的基礎上，提出了高速混合濾波器組adc系統。
  7. The measurement system consist of computer, 16 - channel high speed data acquisition board, spark plug pressure sensor, crank angle signal generator, charge amplifier and oscillograph. the max acquisition frequency of this system is 1mhz

    由通用微機、 16通道無相差高速數據採集卡、火花塞式壓力傳感器、角標信號發生器、電荷放大器、示波器組成的高速數據採集系統，最高總采樣頻率為1mhz 。
  8. Up to 8 mb of megazoom deep memory come standard so you can capture long, non - repeating signals, maintain high sample rate, and quickly zoom in on areas of interest

    高達8mb的megazoom深存儲器，使您能捕獲很長的非重復信號，保持高采樣率並能快速放大所關注的區域
  9. In such situation, controlling of the transf - orming process and synchronizing of sampled data only could be achie - ved via hardware, and data must be stored ( by using high - speed stora - ge chip ) and digital signal must be processed ( by using high - speed d - sp ) in real time simultaneously

    在這種情況下，通常只能用硬體實現轉換過程的控制和采樣數據的同步，仔細設計時序電路，同時必須採用高速存儲晶元對數據進行存儲和高速的數字信號處理器（ dsp ）完成數字信號的實時處理。
  10. The pulse - peek sampling and adc module is able to catch a single and very narrow pulse in order to sample its peek value without being influenced by other pulses or noise. the pulse - peek sampling and adc module can also adapt itself to different rising edge of pulses, so it can scale different types of explorers made by our research institute

    X射線探測器定標分析系統的前端脈沖峰值採集及其轉換電路能夠實現單個快速脈沖的捕捉及對不同脈沖上升沿陡緩的適應，它對不同傳感器的放大信號特徵都有很好的適應性，對脈沖峰值采樣的結果具有很高的精度。
  11. A high - speed sampling system for echo signal of impulse gpr based on equivalent time sampling method is presented, and significant circuits including step sampling pulse generator and sampling gate circuit are designed

    摘要提出了一種基於等效時間采樣方法的沖擊型探地雷達回波信號高速采樣系統，設計實現了等效時間采樣的關鍵電路，包括步進采樣脈沖發生器、采樣門電路。
  12. Measure and control unit adopted 16 - bit, high - speed a / d converter, it can guarantee the speed and precision of alternating sample. the part of communication adopted can bus to transmit the data, it was suitable for real - time control and can guarantee dependability. it adopted the can bus adapter of yan - hua company whose type was pcl - 841 to communicate with processor unit the processor unit adopted industrial pc, which can guarantee the system work well for a long time

    其中下位裝置採用西門子公司的高性能十六位處理器c167cr - lm ，其內嵌can總線控制器便於通過can總線與上位機進行通訊，數據採集部分採用十六位高速a d轉換器從而保證了交流采樣的速度與精度，通訊部分採用可靠性高，適于現場實時控制的can總線來傳輸數據，與上位機介面採用研華公司的型號為pcl - 841的can總線適配器，為保證系統長時間可靠運行上位機採用工控機。
  13. With regard to the flow regulation of the best - effort traffic, the controllable traffic in high speed computer communication networks, the present paper proposes a novel control theoretic approach that designs a proportional - integrative ( pi ) controller based on multi - rate sampling for congestion controlling. based on the traffic model of a single node and on system stability criterion, it is shown that this pi controller can regulate the source rate on the basis of the knowledge of buffer occupancy of the destination node in such a manner that the congestion - controlled network is asymptotically stable without oscillation in terms of the buffer occupancy of the destionation node ; and the steady value of queue length is consistent with the specified threshold value

    本文從控制理論的角度出發，針對計算機高速網際網路中最大服務交通流即能控交通流的調節問題提出了一種基於多速率采樣的具有比例積分（ pi ）控制器結構的擁塞控制理論和方法，在單個節點的交通流的模型基礎上，運用控制理論中的系統穩定性分析方法，討論如何利用信終端節點緩沖佔有量的比例加積分的反饋形式來調節信源節點的能控交通流的輸入速率，從而使被控網路節點的緩沖佔有量趨于穩定;同時使被控網路節點的穩定隊列長度逼近指定的門限值。
  14. In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower

    在時域，根據數字示波器隨機取樣原理，用兩種方法（雙斜率積分時間放大測量方法和時間? ?電壓轉換測量方法）測量數字示波器系統觸發和采樣寫時鐘間時間間隔，用低速a / d轉換器及控制器進行模?數轉換和控制，以此進行隨機取樣內插，從而實現了對高頻率重復信號的測量。
  15. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  16. Dsp56f805 samples the ultrasonic pulse coming back from the target, then measures the distance and shows it on led. tms320vc5509a is accomplished the detecting speed and the main control of the radar system, is 16 fixed dsp with high performance and low power produced by ti company. dsp5509a samples the wave coming from t / r module, then measures the target ’ s speed and send this information to the assistant control chip - p89v51 based on boost c51 core mcs produced by philips company, which controls the lcd

    測距雷達系統的控制和信號處理的核心晶元是motorola公司的dsp型16位單片機56f805 ，由它對超聲波回波脈沖進行ad采樣后，計算目標距離並在七段數碼管上顯示。測速雷達系統中信號處理的核心晶元是ti公司的超低功耗、高性能的16位定點dsp ? ? tms320vc5509a ，由它對收發組件輸出的多普勒回波進行采樣，計算出目標運動速度后，送給輔助控制晶元? ?飛利浦公司生產的基於c51內核的增強型單片機p89v51 ，並且在液晶顯示器上顯示速度信息。
  17. In this paper design of some circuit including in a / d circuit is also analyzed, such as front analog circuit, sample clock circuit and data flip - latch circuit

    同時對高速轉換器件及轉換電路中包括前端模擬電路、采樣時鐘、後端數據鎖存等輔助電路設計進行了分析。
  18. Using the high - performance digital signal processor ( dsp ) as cpu, the author designs the medium - speed sampling and processing unit of the fault locator. on the one hand, this unit can sample voltages and currents of the line synchronously ; on the other hand, this unit can start the fault locator up and select the fault lines when faults occur

    本文作者還以高性能的數字信號處理器（ dsp ）為cpu設計了測距裝置的中速采樣處理單元，該處理單元一方面可以實現線路電流電壓信號的同步數據採集，另一方面可以完成測距裝置的故障啟動和故障選線任務。
  19. Abstract : the control reconfigurable aircraft with multi - surfaces needs robust basic flight control system to support enough time for failure detection and isolation. when partial surface loses, it can keep the damaged aircraft stable. in this paper, multivariable output feedback digital control laws are designed for the control reconfigurable aircraft ( cra ). the method uses fast - sampling digital pi controllers to design digital flight control tracking system. this paper gives the way to design the controller and analyze its robustness characteristics. the simulation results indicate that the controller is very robust and the output responses are fully satisfactory

    文摘:控制可重構飛機要求其基本飛行控制系統對舵面部分缺損故障具有強的魯棒特性，在故障發生后保證飛機的穩定性，提供足夠的時間進行故障的檢測和隔離，為控制系統重構提供條件.本文採用高速采樣pi控制器設計輸出反饋跟隨系統，給出了控制器的設計方法，並分析了它對于控制舵面部分缺損故障的魯棒特性.模擬結果表明，這種控制器具有好的魯棒特性
  20. The delta operator is introduced to the h9 filter problem of discrete system, which is significant for the anti - disturbance of the high - speed sampled system. in the delta domain system, the coefficient of the gain matrix of the estimator is approaching to that of the continuous - time system. which not only guarantees the stability and the performance of the system but also avoids the also avoids the defects the z domain when the sampling periods is approaching to zero

    濾波問題中，這對于高速采樣系統的抗干擾及狀態估計具有很大的理論及實際意義，當采樣周期趨近於零時，估計器的反饋增益矩陣及閉環極點趨近於連續系統的反饋增益矩陣及閉環極點，從而可以採用離散的設計方法獲得連續系統的性能，既保證了系統的性能及穩定性，又避免了z域內設計的缺點。
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