architecture of microprocessor 中文意思是什麼
architecture of microprocessor
解釋
微處理機結構- architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
- of : OF ＝Old French 古法語。
- microprocessor : n. 【計算機】微處理器。
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Prior to google, alan spent 15 years at digital compaq hp s western research laboratory where he worked on a variety of chip design and architecture projects, including the microtitan floating point unit, bips the fastest microprocessor of its era
在他加入google之前， alan在digital compaq hp的西部研究室工作了15年，致力於各種晶片的設計及製造專案，其中包括當時最快的微處理器： microtitan floating point unit ， bips 。 -
Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer
超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。 -
At first, the theory of the strap - down attitude heading reference system is presented and the architecture and algorithm selections are done according to require for low cost. then, the feature and application methods of the new type microprocessor - dsp are explicated, and the design method for dsp and peripheral circuit and the development method for ahrs software are discussed
文中首先討論了捷聯航姿系統的原理，並根據低成本的要求確定捷聯航姿系統模型和演算法，接著分析了dsp這種新型微處理器的特點和應用萬法，討論了dsp及其外圍電路的設計方法與航姿軟體的開發方法。 -
But traditional fieldbus has been widly used in factory field and will act an important part for a long time, so it is necessary that to realize fieldbus connect to office network, make it has the capability of inter - connection and inter - operation, and keep it ’ s architecture unchanged. the paper discusses a method to slove the problem. that is making use of ethernet / ip protocol which is one of industrial ethernet protocols, to design an embedded fieldbus gateway. the gateway mainly consists of s3c2410, a 32bit high performance microprocessor based on arm core, to realize interconnection devicenet network, controlnet to ethernet
本文提出利用高性能、低功耗32位risc結構的arm處理器與armlinux嵌入式操作系統相結合，並利用ethernet / ip工業以太網協議構造嵌入式網關，實現設備的現場總線與企業信息網路無縫鏈接，並保證了devicenet和controlnet兩種網路的互操作性，構建一個可跨地域共享、便於實現高層次集中管理、監控和決策的新型嵌入式實時在線監控網路。 -
Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly
因本課題意在實現微處理器的基本結構，並未涉及到編譯器，因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。 -
The microprocessor architecture design has entered the era of thread level parallelism
目前微處理器系統結構設計已經進入線程級并行的時代。 -
Through the analysis of petri net models and the experimental data gained from eda tools, it is proved that the mix - execution of scalar and vector instructions " architecture is suitable for embedded microprocessor
通過petri網模型分析與eda工具的實驗數據，證實標量向量混合執行模型適用於嵌入式微處理器的體系結構設計。 -
This paper analyze the architecture of amex86 microprocessor, including the analyzer of instruction system, addressing mode, scheduling and clock of instruction, the integration and validation of amex86 architecture. this paper mainly discusses the design and realization of data path and instruction decoder in detail
本論文將對amex86體系結構的微處理器進行體系結構分析，包括指令系統的分析、尋址方式的分析，指令時序以及指令時鐘拍數的分析和amex86系統的集成及驗證等。 -
This scheme fully considers the internal structure of jx5 microprocessor, at the same time, the processor ’ s processing ability, address and data bus architecture is efficiently utilized. so with the minimal testing cost, a strong fault testing and trace debugging ability is provided to meet the jx5 processor ‘ s testing demand
該方案充分考慮了jx5的內部結構，有針對性的選擇了一系列成熟可靠的可測性技術和方法，經過精心組合搭配，並充分利用jx5所具有的處理能力和cpu特有的地址、數據總線結構，在盡量少的增加測試開銷的前提下，提供了很強的故障測試和追蹤調試能力，很好的滿足了jx5對測試的需求。 -
The features of instruction set architecture and application programs are the key factors to microprocessor architecture
指令系統和應用程序的特點是決定微處理器體系結構的關鍵因素。 -
This paper, first, studies the performance and architecture of high performance processor pipeline, and the technology that used to deal with the correlation and interrupt in pipeline. the author takes part in study and design of pipeline of armp, which is a 32 - bit embed microprocessor
本文首先研究了高性能處理器流水線的性能與結構以及對相關和中斷的處理等關鍵技術，作者作為設計人員參與研究並設計了32位嵌入式微處理器apmp的流水線。 -
13 taylor m b et al. evaluation of the raw microprocessor : an exposed - wire - delay architecture for ilp and streams
目前有兩種支持多種并行模式的途徑，一種是mode ，一種是modeless 。 -
The dissertation focuses on the research and design of 32 - bit microprocessor architecture
本論文的研究課題是32位嵌入式微處理器的體系結構的研究與設計。 -
The work in this dissertation is part of national 05 " project entitled " high performance microprocessor architecture "
本論文的研究內容是受到國防十五預研課題「研究高性能微處理器系統結構」的一部分。 -
Research and design in microprocessor architecture can promote the development of our national ic industry and satisfy market demand
微處理器體系結構方面的研究和設計，可以推動我國集成電路的發展，滿足信息產業發展的要求。 -
Linux for the power microprocessor architecture is an exciting development in the linux story and a testament to the continuing evolution of linux
用於power微處理器體系結構的linux是linux發展中的一個令人興奮的成就，並且指明了linux以後的演化方向。 -
A hierarchical control architecture is adopted, which comprises of a microprocessor level and a pc level and communicates through blue - tooth between two levels
採用了微控制器和pc機兩級控制體系，兩級間採用藍牙通訊。 -
This dissertation gives the detailed analysis of modern dsp processors. on the basis of previous research done on the microprocessor, it proposes the dsp - oriented architecture, which improves the execution efficiency of dsp applications
論文分析了當前數字信號處理器系統結構的發展，結合以往進行的處理器研究工作，提出了針對dsp應用特點的處理器系統結構。 -
Test and simulation of amex86 architecture. the dissertation work plays a great significance for studying the military microprocessors with own intellectual property. the research work offers design considerations and technological reserves for further advanced microprocessor designs with amex86 architectures
本文在系統分析的基礎上針對該amex86體系結構的特點提出了三總線結構的數據通路，為更好的實現指令間流水提供了有效的保障。
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