buffer circuit 中文意思是什麼
buffer circuit
解釋
緩沖電路-
In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail
文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。 -
By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability
然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。 -
Every column in sensor array work in parallel and have their own cds noise reducing circuit. the signals after fpn reducing are output from the output buffer amplifiers
傳感陣列中各列感光單元的傳感信號并行輸出，分別由對應的相關二次采樣電路進行降噪處理，去除固定模式噪聲后的信號通過輸出緩沖放大電路進行輸出。 -
The circuit design of data buffer based on 386dx
處理器的數據緩沖器電路設計 -
The hardware of the system is composed of a high - speed optical - isolator circuit, a first - in / first - out dual - port memory buffer circuit, a pci interface chip ql5032, and a logic control circuit
系統的硬體部分是由高速光電隔離電路，雙埠fifo存儲緩沖電路， pci總線介面電路ql5032及邏輯控制電路等組成。 -
The push - pull mode switch power supply is chosen as the main circuit of the other voltages with pwm control circuit, over - current protection circuit, insulated drive circuit, mosfet buffer circuit and so on
採用高效的推挽式電路作為中低壓電源的主電路，並以pwm控制電路、隔離式驅動電路、過流保護電路、 mosfet緩沖電路、軟啟動電路、穩壓電路等作為輔助電路。 -
An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束 -
Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function
本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。 -
Simulation research and analysis on undeland buffer circuit
緩沖電路分析及模擬研究 -
Socket function mainly realizes setting up and initializing service unit socket, initializing service unit and service unit serial and so on. bind funcion primarily binds local address and port for the socket. listen function is to evaluate the max length of server ’ s listening queue. connect function and accept function set aside rate ahead, infrom user ’ s request of establishing virtual circuit to suna, cooperate with suna to establish the connection between client and server, return the result. we make use of three handshake with data protocol and virtual circuit mode, in this way, when we translate data, we can look up communication course according to virtual circuit number, at the same time, there aren ’ t source ip address and port, end ip address and port in the head of data package, the speed of translating data advances in a certain extent. send function and recv function is to send data collaborating with suna, and copy data from the receiving queue of socket to user ’ s buffer. close function cooperate
Socket （ ）函數實現創建、初始化服務元套接字，初始化服務元及服務元序列等。 bind （ ）函數為套接字綁定本地地址和埠號。 connect （ ）和accept （ ）函數主要是根據用戶要求預留帶寬，將用戶的建立虛電路請求轉達給服務元網路體系，協作服務元網路體系採用捎帶數據的三次握手協議建立虛電路，並告訴用戶處理結果，一方面，捎帶數據的三次握手協議在一定程度上可提高數據傳輸速度;另一方面，採用虛電路方式，使得數據通信可直接根據虛電路號查找相應的通信進程，而且數據包的包頭中省去了源ip地址、埠號和目的ip地址、埠號，提高了數據傳輸速率。 -
The current in the dac ’ s output can drive the load, and the structure can save a buffer consisted of operational amplifier, so the structure can achieve high speed with no close - loop and feedback in this circuit
該10位分段式電流舵型數模轉換器的輸出端可直接用電流輸出來驅動負載阻抗，省去運算放大器構成的輸出緩沖，整個電路中沒有形成閉環和反饋，因此這種電路結構可以達到很高的速度。 -
It has been shown by our calculations that conductor loss is greatly reduced under velocity matching with relatively thick coplanar waveguide electrodes and thick buffer layer, but the characteristic impedance can not match with that of the external circuit at the same time, and the modulation bandwidth is confined in this case
然後，用一般的橢圓積分計算了普通共面波導型調制器的有效折射率、特徵阻抗和導體損耗系數。通過計算發現，採用厚電極和厚緩沖層結構，在實現速度匹配的情況下，可以大大減小導體損耗，但是由於阻抗不能同時滿足匹配，調制帶寬受到限制。 -
Secondly, the dynamic storage module designed by our institute is used to design the buffer of the module, which provids the mass storage space for data acquisition, simplifies the design of circuit board and control circuit of the module, meanwhile, provides the solution to the application of huge capacity continuous acquisition
2 .在模塊的緩存設計上採用所內自行研製的大容量動態存儲模塊，為數據採集提供了大量的存儲空間，簡化了模塊電路板和控制電路的設計，同時，也為大容量連續採集應用提供了解決方案。 -
An output buffer amplifier used in detection circuit of micro sensor
用於微傳感器讀出電路的輸出緩沖放大器 -
The main electric circuit uses integration microprocessor and ic, few buffer circuit for stable operation
主要功能電路採用集成度很高的單片機，外圍電路很少，工作更加穩定。 -
Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired
在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
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