bus interface logic 中文意思是什麼

bus interface logic 解釋
總線介面邏輯
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  • interface : n. 分界面，兩個獨立體系的相交處。vt. （-faced, -facing） 把界面縫合。vi. 交流，交談。
  • logic : n. 1. 邏輯，理論學。2. 推理[方法]；邏輯性，條理性。3. 威力，壓力，強制（力）。
  1. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  2. Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。
  3. Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。
  4. In the thesis, based on design and implementation of the two signal processing system of different requirement, multi - dsp processor structure, dsp - pci interface, system control logic, pci device driver program, user application program are researched. the main content is list as follows : 1 ) according to the lfmcw radar signal processing algorithm, a signal processing system based on pc104 - plus bus is developed

    本文通過對以上兩種雷達信號處理機的設計開發過程，研究了採用多片dsp信號處理器組建并行處理模塊實現信號處理演算法的方法，利用pci總線實現處理機數據傳輸介面，設備驅動程序和控制界面軟體開發，實現信號處理機數據傳輸控制等幾個方面的內容，主要工作如下: 1 ）針對線性調頻連續波雷達信號處理演算法，完成了基於pc104 - plus總線的嵌入式信號處理板的設計、製作以及調試。
  5. The digital upward frequency conversion is the key element of the waveform synthesis. at the same time, basic theoretical analysis and optimum design are done for pci bus slave interface, fifo, transmit signal processor, digital - to - analog converter and logic control

    本文對波形合成技術的核心? ?數字上變頻進行了深入細致的研究和介紹，同時對波形合成器中的pci總線介面、先進先出緩沖器、發射信號處理、數模轉換及邏輯控制等部分進行了分析和優化設計，給出了最佳設計方案。
  6. The logic analysis and circuit design of vme bus interface iogic

    總線介面邏輯分析和電路設計
  7. According to the necessity of cpci - gpib controller interface module, analyzing the cpci bus, gpib bus and interface function in detail, the design accomplished the function of bridging connection, conversion of protocol, logic control and so on

    本文根據設計cpci - gpib控制器介面模塊的需要，在詳細分析cpci總線、 gpib總線協議及介面功能的基礎上，完成了設計任務，並實地驗證了cpci與gpib總線之間的橋接、協議轉換、邏輯控制等功能。
  8. Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache

    後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。
  9. The interface logic between the add - on bus of s5933 and the host interface of sharc is designed and realized. 3

    Pci介面控制晶元s5933與sharc的hostinterface的介面邏輯的設計與實現。
  10. 2. by using fpga and the vhdl hardwa - re descriptive language, the interface logic between the add - on bus of s5933 and the host interface of silarc is designed and realized. 3

    採用fpga器件，並利用vhdl語言完成邏輯設計pci介面晶元s5933的add - on總線與sharc的hostinterface的介面邏輯。
  11. Ql5030, to implement the design of the interface chip. the pci interface controller and programmable logic were integraed in ql5030 chip. on the basis of the profound comprehension of pci protocol, we designed the bus configuration, data transision logicand self - test logic by using the languge such as vhdl. verilog

    Ql5030內集成了pci介面控制器和用戶可編程邏輯fpga 。本設計在深刻理解pci協議的基礎上，在用戶可編程邏輯fpga上，應用硬體描述語言vhdl 、 verilog ，設計了總線配置空間、數據傳輸邏輯和閉環自測試邏輯。
分享友人
分享到 Line

分享到臉書