chip area 中文意思是什麼
chip area
解釋
基片面積-
What cries blue chip ? with red prepare what is the area
什麼叫藍籌股？與紅籌股的區是什麼？ -
In oilfield, feeder line of 6kv often has many branches. the pole high voltage automotive capacitor compensation system controlled by single chip computer is designed for this situation. in the system, we separate the measure position and compensation position and realize the supervision of reactive load in local area
文章以油田6kv輸配電線路為例，針對多分支樹狀結構線路的特點，研製出由單片機系統控制的戶外術上型高壓電容器自動補償系統。 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
With its new frame. modern technology, complex information dispose and unique control mode, it embodys an idea which is information centralized and control decentralized. its main advantage is system open and interchange and its frame is so simple that it can decrease producative. cost and maintenance load. as it is a new technology, there are different kind databus standards which adapt to different control area. this papaer firstly introduces field bus ' sframe work, function, type, compares distributed control system and field control system. then it focuses on introducing can protocol and can control chip sja1000 and can interface chip 82c250, at last, it introduces how to set up a typical automatic control model based on can. this model can be used in practical industrial control area and management area by appropriate change
由於現場總線是一門新技術，有各種不同的總線標準和總線形式，它們適用於不同的領域，本論文首先分析現場總線的體系結構、功能、類型，比較集散控制系統與現場總線控制系統的區別，然後集中論述了其中的一種現場總線? ? can總線（ controllerareanetwork ） 。介紹了它的協議規范，並且介紹了現在比較流行的can控制器晶元sja1000和can介面晶元82c250 ，並在此基礎上，組建了一個典型的基於can總線的自動化模塊控制模型，把這個模型進行適當的改動就可以用於實際的工業控制領域和管理領域中。 -
And the results of calculation and numerical simulation indicate, without increasing the intrinsic collector - junction area of power devices, collector - combed structure helps to raise the intrinsic heat - dissipating area and base ' s perimeter, improve heat - dissipating method of each cell of the chip, enhance the distribution uniformity of junction temperature and current of each cell of the chip, reduce the thermal resistance and raise the dissipation power pd and output power p0, fairly well relax the contradiction among frequency, out - put power and dissipation power of the devices, and further improve the devices " property against second breakdown
而計算分析和二維數值模擬分析結果表明：梳狀集電結（基區）結構在不增加器件本徵集電結面積的條件下，增大了器件的本徵散熱面積和基區周長，改進了每個子器件單元內的散熱方式，提高了單元內結溫和電流分佈的均勻性，降低了器件的熱阻，增大了器件的耗散功率和輸出功率，較好地緩解了目前傳統結構中頻率與功率、功耗的矛盾，並有利於改善器件抗二次擊穿的性能。 -
Prediction of the breaking area of 3 - d chip former using rbf neural networks
神經網路在可轉位三維槽型刀片斷屑范圍預測中的應用 -
Firstly, based on conventional vq, a fast algorithm named equal - sum block - extending nearest neighbor search ( ebnns ) is presented, which not only can achieve the reconstructed image of full search algorithm but also can greatly reduce both the codeword search ratio and chip area. in order to improve coding efficiency, a new algorithm called correlation - inheritance coding is proposed, which is embedded in conventional vq system to improve compression ratio by re - encoding the indexes
首先，在普通矢量量化基礎上提出了等和值塊擴展最近鄰快速碼字搜索演算法（ ebnns ） ，該演算法在圖像畫質達到窮盡搜索演算法的前提下，大大降低了碼字搜索率和硬體實現面積；為了提高編碼效率，在相關性編碼方面，提出了相關繼承編碼演算法，對普通矢量量化后的編碼索引進行無損重編碼。 -
Being based on actual multi - chips module packaging structure a three dimensional thermal analysis model is built, thermal analysis on multi - chips module is conducted using diamond substrate and thermal interfacial materials ; a two dimensional and three dimensional chip - adhesive ? substrate thermal stress model are built, and interfacial thermal stress distributions are computed based on different area ratios and thickness ratios of substrate to chip
本文根據實際的多晶元組件的封裝結構，建立了三維溫度場分析模型，分析了金剛石作為導熱層和基板對多晶元組件散熱性能的改善;建立了二維和三維的晶元-粘結層-基板熱力學模型，分析了不同的基板/晶元厚度比和面積比對層間熱應力分佈的影響。 -
So in one hand it requires the wafer ' s diameter to be more large in order to enhance the productivity, and on the other hand it puts forward more strict requirement about the crystal perfection and electricity character. especially the electronic character and the equality of micro - area in the crystal wafer has become the key factor to determine whether the device can be made on it or not. so the resistivity measurement of micro - area become one most important procedure in the chip machining. to ensure the produce quality of chip and the perfect performance of final production, the four - probe testing technology need to be deeply studied
圖形日益微細化，電路尺寸不斷縮小，目前ic製造以8英寸、 0 . 13 m為主，預計在2007年左右將以12英寸、 65nm為主，這一方面要求圓片直徑不斷增大以提高生產率，另一方面對晶體的完美性、機械及電特性也提出了更為嚴格的要求。特別是微區的電學特性及其均勻性已經成為決定將來器件性能優劣的關鍵因素。因此，微區電阻率的測試成為晶元加工之中的重要工序。 -
In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed
其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。 -
But large quantity of memory is often used and the area and power of the memory units usually hold the largest percentage of the whole chip
片內存貯器件過多導致存貯器件的面積和功耗大大增加。該論文以ac3音頻解碼程序為例，提出了soc中存貯優化的一般方法。 -
The bias voltage in the circuit is supplied by the bgr, which reduces the power consumption and the area of the chip. this paper takes polygon interpolation as non - linear calibration method, adopts hdl verilog to design the digital duty cycle measuring circuit, from which we have obtained a group of
選擇了臺積電0 . 25 mcmos工藝庫，利用hspice模擬工具對整個溫度傳感電路進行模擬測試，結果顯示所設計體溫計在30 c 50 c的溫度范圍內具有0 . 01 c以上的檢測精度、 0 . 1 c的顯示精度和180 w的最小功耗。 -
This paper research the principle of two dimensional collimator system in which the area - array ccd, cpld circuit and dsp chip are used. digital acquisition and processing hardware and software were designed. the test result was given
本文研究了用cmos作為接收器件，用cpld電路和dsp晶元進行系統流程式控制制和數據處理的二維變形測角儀的系統原理，設計了數據採集、處理的硬體軟體，並進行了實驗。 -
Its circuit structure is very complex and its chip area is restricted severely by the client
其電路結構十分復雜，而且客戶又對版圖面積做了詳細的規定。 -
Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches
速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。 -
The chip area and power savings of not implementing floating - point in hardware can be critical in embedded microprocessors
在嵌入式微處理器中，硬體中省去浮點（支持）而為實現帶來的晶元面積和功率的減少是至關重要的。 -
The dual mode transmitter can be configured in voltage mode supporting 12mbp / s data rate or current mode supporting 480mbp / s data rate. it reduces greatly the chip area resulting from this architecture
雙模發送器的設計，採用電壓模式和電流模式實現了全速（ 12mbp s ）和高速（ 480mbp s ）模式的兼容，取代了傳統的全速和高速發送器分開設計的模式，大大節省了晶元的面積。 -
Since the multiplication calculation cost more chip area than add calculation and the floationg - point calculations are not efficiently implemented in custom hardware they were replaced by scaled fixed - point approximations. also the jpeg coding algorithm requires a substantial amount of memory
本設計只在dct變換部分實現了必要數目的乘法器，通過採用特定的量化表避免了在量化模塊中進行除法運算，大大減少了乘法器的數量。 -
At the logic synthesis stage, we make some research on the principles of logic synthesis at first, then by utilizing tsmc0. 25um process, choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2. 25v, and introducing the wireload library for effectively simulating delay and power consumption of wire connection, and taking the same clocks as in simulation, the critical path is 15. 3ns and the chip area is 0. 395mm2
在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然後利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，採用與模擬時相同的時鐘，關鍵路徑為15 . 3ns ，晶元面積為0 . 395mm ~ 2 。 -
The hspice simulation result shows a temperature coefficient of 11 ppm / " c from - 40 ? to 100 ' c and output voltage variation of 1mv for supply voltage range from 8 v to 18 v. due to novel curvature compensation, the circuit structure of the proposed reference is simple and both chip area and power consumption are small
Hspice模擬結果顯示：該基準源在- 40 100的溫度變化范圍內，具有11ppm的低溫度系數；當電源電壓在8 18v變化時，輸出電壓變化量僅為1mv ；並且電路結構簡單，具有較小的晶元面積和功耗。
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