decode unit 中文意思是什麼
decode unit
解釋
譯碼單元-
The control system included the following units : video decode unit, data format conversion unit, fpga controller, cache unit and d / a monitor. the above self - design control unit plus row and column power supply units make the whole fed driving system, thus drove the 25 inch sample and realized color video display. the 25 inch vga sample thus fabricated could display video images, and obtained its brightness 400cd / m2, contrast ratio 1000 : 1, 256 circuit gray scale
本文介紹了fed驅動系統的工作原理，重點論述了基於fpga的vga級彩色fed新型驅動控制系統的研製，這種新型fed驅動控制系統主要包括視頻解碼電路、數據格式轉換電路、 fpga控制電路、數據緩存電路和d / a監控電路，配合后級列灰度調制單元和行掃描單元，組成完整的fed驅動系統，可以驅動25英寸vga級fed顯示屏，實現彩色視頻顯示，樣機亮度達400cd / m2 、對比度為1000 : 1 ，灰度等級為256級。 -
The catv charge and control system is mainly composed of the management software 、 the header data modulator and the terminal charge and control equipment. i am responsible for design catv charge and control equipment and test system. the header data modulator is used to encrypt the control single from computer and transmit it into the appointed frequency. the terminal charge and control equipment demodulate out the control single from data modulator and transmit it to the addressing control part, where the demodulated fsk single is received and well - handled by the cpu unit, decode the unauthorized signals and deliver it to the shut point, shut point make use of capability of wideband anf characteristic of shut, then the signal of illegal customer will be turn off and vice versa, the legal customer can receive the normal signal
前端數據調制器完成對計算機輸出的控制信號加密處理，將指令碼載送到一指定頻率點。終端收費控制器解調出控制信號，送至單片機尋址控制部分。單片機尋址控制部分接收經fsk數據解調器送來的信號，送入cpu單元后，解出不授權信號，然後向關斷部分送入信號，關斷部分利用pin二極體的寬帶工作能力以及關斷特性，實現對非授權用戶或者非法用戶的信號關斷，使之不能正常收視，繳費用戶進行開通正常收視，達到控制用戶通道的管理。 -
Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design
Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。 -
The 32 - bit cpu core with enhanced multiply accumulate emac unit provides optimum performance and code density for the combination of control code and signal processing required for mp3 decode, file management, and system control. fs2401clqn is a single - chip mp3 audio decoder
當用戶端的pc與存儲媒介之間透過usb 2 . 0介面做資料交換時，因僅需要cpu最低程度的參與，而大多是以硬體處理方式，所以可以達到高速傳輸的目的。 -
Each unit is extracted from the circuit, and is analyzed detailedly in framework, configuration and design approach. the instruction system of c9821 is unscrambled and then the instruction decode algorithm are obtained. the complete program of c9821 including basic arithmetic and root square operation is realized
在軟體方面，破譯了c9821的指令系統，分析了指令譯碼電路的設計技術，分析了計算器內bcd碼的四則運算及開方運算演算法，得到了實現c9821全部功能的程序，掌握了該計算器的程序設計方法。 -
Since the mpeg - 2 decoding chip is a soc, 32 - bits embedded risc cpu core is used to decode the ac3 and ts bit stream. the risc core is also used to manage the different task in the chip and the video processing unit is realized in asic modules
論文設計的mpeg - 2系統集成解碼晶元是一個soc ，該soc採用32位嵌入式risccpu核virgo進行音頻ac3和ts流解碼的計算任務，並承擔soc的管理；視頻解碼採用asic實現。
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