dynamic cmos 中文意思是什麼

dynamic cmos 解釋
動態互補金氧半導體
  • dynamic : adj 1 動力的，動力學的；力學（上）的；動（態）的；起動的。2 有力的，有生氣的；能動的；（工作）效...
  1. As key technology of the single chip calculator, the highly integrated dynamic cmos logic implement and the micro program design are now owned only by the developed countries and kept in secret. based on the conjunction of " top - down " and " bottom - up " design approach, the hardware system and micro program design of the calculator is thoroughly studied in this paper, and finally has been mastered

    本論文以香港興華半導體公司的計算器單晶元c9821為藍本，採用了自頂向下和從底向上相結合的方法，對計算器單晶元的硬體電路設計和軟體編程方法進行了深入的研究與剖析，終于掌握了這種晶元的設計技術，並對c9821進行了功能的改進與完善。
  2. The pixel size of p + / n - well / p - sub structure is 100 umx 100 n m, fill factor is 77. 6 %. it can obtain target information with illuminance intensity in the range of 0. 011x ~ 98, 0001x, and the sensor photoelectric sensitivity is 35v / lx ? s. when the method of changeable reset frequency double scanning is used, the photoelectric dynamic range can be 139. 8db, which is high in the 0. 6 um level cmos image sensors already reported

    在對感光單元進行器件物理結構優化的研究中，通過採用深結深光電管結構，提高了傳感器的感光響應，其中p m階」襯底結構的傳感器面積為100umx100urn ，感光面積百分比為77石，可對0刀98 ， 000lx照度的目標信號進行傳感，感光靈敏度大於3sv ix ? s ，採用了變頻兩次掃描后，動態范圍可達139
  3. The program deriving dynamic equations runs in puj 800, double cpu, 256 mb memory. the synthesis tool and cmos chip of xilinx company are applied to design the hardware

    本文中的動力學方程推導程序是在p 800 ，雙cpu ， 256兆內存的機器上運行的。硬體的設計是採用xilinx公司的綜合工具與晶元實現的。
  4. The proposed modulator uses 0. 35um standard cmos process, the nmos and pmos threshold voltage is 0. 54 volt and - 0. 48 volt, respectively, and the power supply is 1. 5 volt. the nyquist converter rate is 50 khz, oversampling ratio is 80. the proposed modulator can obtain 98db dynamic range, 16 bits converter resolution, and fits for high - fidelity, digital - audio application

    本設計採用0 . 35微米標準cmos工藝，其中nmos和pmos晶體管的閾值電壓分別為0 . 54伏和- 0 . 48伏，電源電壓為1 . 5伏，奈奎斯特轉換率為50khz ，過采樣率為80 ，該調制器可實現動態范圍98db ， 16位的轉換精度，適合高保真數字音頻應用。
  5. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值
  6. Sparse - tree architecture enables low carry - merge fan - outs and inter - stage wiring complexity. single - rail and semi - dynamic circuit improves operation speed. simulation results show that the proposed adder can operate at 485ps with power of 25. 6mw in 0. 18 - mu m cmos process

    具有代表性的并行前綴進位結構有kogge - stone樹brent - kung樹han - carlson樹和knowles樹等，一些高性能的加法器也由此被設計出來。
  7. Dynamic power is dominant component of the average power dissipation in cmos circuits. and the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of cmos circuits. so most low power designs are achieved by reducing one or more those above parameters

    由於cmos電路的功耗與cmos電路的負載電容，電壓，時鐘頻率及開關活動性有關，因此在低功耗cmos觸發器設計過程中，許多低功耗設計技術都可以歸結到通過減小上面的參數來達到低功耗的目的。
  8. In cmos technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values

    電路的功耗分為靜態功耗和動態功耗，對于cmos電路，功耗主要是動態功耗，大約占總功耗的85 ? 90 % 。
  9. At present testing method based on current testing has become an important cmos digital integrated circuit testing method which has been accepted widely. in order to improve the fault coverage of the testing to meet the demands of people, the dynamic current ( iddt ) testing was proposed to detect some faults that cannot be detected by other testing methods in the middle 1990 ’ s

    90年代中期，人們提出了瞬態電流測試方法（ iddt ） ，以便發現一些其他測試方法所不能發現的故障，進一步從總體上提高測試的故障覆蓋率，滿足人們對高性能集成電路的需要。
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