fast address 中文意思是什麼
fast address
解釋
快速地址-
The system is consist of the main data processing board which is based onthe fpga device and fast ethernet phyceiver rtl8201l and a - law pcm data encoder and decorder chip msm7702 - 3, and the dial - up and display board which is based on mcu. the main board would carry out the core task of data processing, such as voice data packing and unpacking, the ethernet frame processing, protocol processing, call processing, etc. the dial - up and display board would carry out the task of display the ip address which is input by consumer and status of network during talk period from the main board, and so on. in the paper the system of lan ip telephone and the tcp / ip protocol is introduced firstly, then the fpga device is stated. after that the fpga - based hardware scheme is introduced in detail in chapter four
系統以altera公司的acex1k系列的fpga和快速以太網控制器rtl8201l和語音編解碼晶元msm7702 - 3為核心構建了數據處理主板和以單片機為控制器的撥號顯示子板組成。數據處理主板的核心任務，包括語音數據處理、以太網幀處理、協議處理、呼叫處理等。撥號顯示子板則完成通話前的顯示用戶所撥過的ip地址，通話期間網路狀態的顯示等等。 -
Further research will address questions such as whether, during a highly stressful event such as the last minutes of a close football final, people at risk would benefit from added medicine to prevent blood clots, fast heart rate and raised blood pressure that could increase the risk of a heart attack
進一步的研究將立足於這樣一個問題：在一場激烈的橄欖球比賽終場前的最後幾分鐘里，處于興奮中的人們能通過增加服藥量來避免血栓，心率加快和血壓升高等增加心梗可能的癥狀發生。 -
And the various software to print matching call database, fast printing labels apply to box labels, logistics labels address labels, clothing labels, bar code labels
以和各種列印軟體相匹配，調用數據庫，快速列印標簽，適用於外箱標簽，物流標簽，地址標簽，服裝標簽，條形碼標簽等。 -
The average ipc speedup is 5. 9 %. 2. adaptive stack cache with fast address generation policy is proposed by investigating stack access behavior of programs
2 .通過對棧訪問行為的分析，提出一種棧高速緩存方案? ?快速地址計算的自適應棧高速緩存組織方案。 -
Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here
該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。 -
It can also be applied to multithread scheme by adding thread identifier. our experiment results indicate that about 25. 8 % of all memory reference instructions in spec cpu2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. on average 9. 4 % data cache miss is reduced
Speccpu2000程序運行結果表明，採用快速地址計算的自適應棧高速緩存方案， 25 . 8 %的訪存指令可以并行執行，數據高速緩存失效率平均降低9 . 4 % ， ipc值平均提高6 . 9 % 。 -
Secondly, apon needs to address the fast synchronization of burst cells on the uplink
Apon需要解決上行通道中突發信元快速同步的問題。 -
This usage as a form of address from a black to a white man is dead in namibia, where it has been banned by law, and it is fast dying in south africa
這個用法是黑人對白人主人的稱呼，但此用法在納米比亞被法律禁止，因而在那兒已消亡了；在整個南非也在迅速消亡。 -
Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic. stack cache can be disabled adaptively, when it is overflow
該棧高速緩存在發生棧溢出時，能夠自適應地關閉，以避免棧切換對處理器性能的影響。
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