loop lock 中文意思是什麼
loop lock
解釋
環阻-
The results of experiment tell it is an effective method of share current. a strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase - lock loop to track synchronization signal
在同步控制上，應用了「優先與搶占」的方式產生同步信號，純硬體實現，簡單可靠；使用了成熟的數字鎖相環來跟蹤同步信號。 -
It introduces the method of modulated light subtracting infrared radiation of atmosphere and background as well as the method of phase - lock - loop detecting feebleness signal
採用光路差分調制的方法實時扣除背景紅外輻射，並採用鎖定放大器進行微弱信號的檢測。 -
In this paper, a ku band frequency source based on sampling phase lock loop technique is introduced. the vco of the loop is designed using dielectric resonator. the theory and design method is discussed and emphasized on
本文介紹了一個應用取樣鑒相和鎖相原理製作的微波ku波段頻率源（頻率合成器） ，其中的壓控振蕩器部分是用介質諧振器（ dr ）設計的。 -
3 using current injecting frequency modulation method and modulating sine wave around the resonator point, the lock - in phenomena is observed in a comparatively short period of time. this has achieved the basic goal for a closed loop r - fog
3 、採用電流注入法，在諧振點附近進行正弦調制，實現了對諧振點的短時間鎖定，達到了閉環光纖陀螺設計的首要基本要求。 -
The principle of large step fast acquisition and the circuit design of large step fast acquisition delay lock loop ( lsdll ) are disgussed as the emphasis
本文著重從理論和電路設計兩方面對大步進快速捕獲方法和大步進快速捕獲延遲鎖定環進行討論。 -
This paper based on control theory, according to the conception of phrase lock loop and direct digital synthesis, we designed the clock circuit. it realizes the amalgamation of kinds of the ways about clock, which make it has some superiority
本論文在控制理論的基礎上，以鎖相頻率合成和直接數字頻率合成作為設計思想，搭建時鐘控制電路，在業界實現了多種時鐘控制電路實現方法的融合與統一，具有一定的優越性和領先性。 -
Through the research of direct digital synthesizer ( dds ) used as a divider in phase lock loop ( pll ), a frequency synthesizer with small frequency resolution ratio and high purity frequency spectrum can be realized
摘要通過對直接數字合成器在鎖相環路中作為分頻器應用的研究，使頻率合成器可以在實現超細頻率解析度的同時達到高的頻譜純度。 -
In the traditional polarization diversity and combining scheme, differential mode loop and common mode loop is combined to lock in the phase and frequency of the diversity signals and remove the carrier frequency bias and doppler shift
傳統的極化分集接收方案是將差模環和共模環相結合完成兩路信號的同頻同相鎖定以及多普勒頻率偏移的去除。 -
In this paper, consulting the idea of software radio and using the three important theories of maximum mean power estimate ( mmpe ) for symbol synchronization algorithm, the kalman decision - feedback equalization ( dfe ) algorithm and the decision - feedback phase lock loop ( dfpll ) algorithm, a kind of low frequency digital demodulate scheme over high - frequency ( hf ) radio channels for 8psk signial is realized
本文利用軟體無線電的思想，提出了一種hf通道8psk信號低頻采樣數字化解調方案。討論了實現該方案的三個核心演算法：最大平均功率定時同步演算法、判決反饋式鎖相環和卡爾曼均衡器，分析它們的基本理論，並進行了性能測試。 -
This dissertation is based on the theory of phase lock loop ( pll ) and the design of frequency synthesizer, and the summing up of the work on the microwave and millimeter wave ( mm ) frequency synthesizer
本文是在充分了解鎖相環（ pll ）的理論和各種頻率合成技術的基礎上，對微波毫米波頻率綜合器的理論探索和實際研製工作的總結 -
The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product
本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型；較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性；重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究；為了改善環路的捕獲性能，對擴捕電路進行了分析和設計，並用wewb32軟體對電路進行了模擬；考慮到取樣保持器的附加相移影響，對環路濾波器進行了分析和設計。 -
Phase lock loop
相鎖迴路 -
In this paper, a pll frequency synthesizer working in l band is researched. at fist, we review the basic of phase lock loop and it ' s constituent part. after that the basic conception and design method of pll frequency synthesizer was introduced, especially introduced the charge pump pll frequency synthesizer in detail
本文是採用鎖相原理設計的l波段頻率合成器，首先對鎖相環路的工作原理和基本組成部分進行了簡單的介紹，然後介紹了鎖相頻率合成器的原理和設計方法，主要介紹了目前小型頻率合成器產品中使用最廣泛的由電荷泵數字鑒頻鑒相器和無源環路濾波器構成的頻率合成器。 -
Then according to the emphasis of the design, went deeply into the theory of pll frequency synthesizers widely used, described pll ’ s working principle, structure and several types in detail, and made research and analysis of pll frequency synthesizers ’ phase noise, including the effect of the active loop filter on the phase noise, and give some methods to make improvement as well, such as changing loop filter form, reducing divide number, and increase phase detector frequency, etc. then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit, which are also important circuits in the design
論文首先對幾十年頻率合成器的發展進行概述，而後針對本次設計的重點，對應用較為廣泛的鎖相頻率合成理論進行了深入的探討，詳細介紹了鎖相環的工作原理、組成結構和鎖相類型，並對鎖相頻率合成器的相噪特性進行了研究分析，包括有源環路濾波器對于相噪的影響，提出了改善相位噪聲的幾點措施:改善環路形式、降低分頻數、增大鑒相頻率等。接著介紹了直接數字頻率合成器（ dds ）和注入鎖相電路的原理特點以及相噪分析，它們也是本次設計的重要電路。 -
A zero - voltage starting method is brought forward which switch the starting from separate exciting to self - exciting successfully ; pll ( phase lock loop ) technology is employed to realize the frequency tracing and constant phase angle control ; igbt driving and protective circuit suitable for parallel inverter is developed, which successfully solve the problem of time compensating and overlapping regulation for the driving signals ; a novel and practical over - voltage protective method for parallel inverters is presented which effectively avoid the possible over - voltage destroy to the inverter. xu haiwen ( power electronics and electric driving ) directed by senior engineer peng yonglong
提出了一種零壓啟動的他激轉自激方法；通過採用鎖相環技術實現了逆變器工作頻率的自動跟蹤和容性逆變角度的恆值控制；設計了適用於並聯諧振型逆變器的igbt驅動與保護電路，解決了驅動信號的時間補償以及重疊角的可調問題；提出了一種新穎、實用的逆變器過壓保護方法，有效地解決了並聯型諧振逆變器過壓保護這一難題。 -
Digital phase lock loop is used in this section to synchronize to an incoming serial data stream
數據接收解碼模塊中使用了數字鎖相環技術從輸入數據碼流中提取出同步時鐘信號。 -
Pll : phase lock loop
階段鎖定 -
A kind of accurate automatic gain control circuit based on phase lock loop
基於鎖相環的精確自動增益控制電路 -
In the control loop, the phase - lock loop was used to trace the operating frequency, the vibrating - amplitude loop was used to control the driving influence, the compensate control loop was used to adjust balance, and the measuring loop was used to measure. with the simulation charts of various subsystems, the system parameters were designed
在控制迴路中，利用鎖相迴路來追蹤工作頻率，用振幅控制迴路來控制驅動力，用補償控制迴路調節平衡，用感測迴路進行感測，並且利用各分系統的模擬圖設計出系統參數。 -
Is unrolled and the method call inlined, the unrolled loop will be a sequence of lock - increment - unlock groups
並內聯該方法調用時，已展開循環的順序將是「鎖-遞增-解鎖」這樣的順序。
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