parallel architecture 中文意思是什麼

parallel architecture 解釋
并行結構
  • parallel : adj 1 平行的；并行的 （to; with）; 【電學】並聯的。2 同一方向的，同一目的的。3 相同的，同樣的，相...
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. In addition, many other problems also exist in hardware neural network, including error problem, learning mode, parallel architecture, and also neural network inner linking problem, hidden layer and the realization of the multiplicator and etc. for instance, error problem : hardware neural network employs the limited precision, and will inevitably bring limited precision error

    另外，硬體實現神經網路還存在誤差問題，學習方式，并行結構等方面的問題，還有神經網路內部的連接問題，隱層及乘法器的實現等等。如誤差問題，硬體實現神經網路使用的是有限精度，不可避免的會產生有限精度誤差，選取合適的精度，才能既適合空間的要求，又避免對網路的實現產生一定的影響。
  2. It preestablish a parallel design pattern for each parallel project based on master / slave architecture, and the communication between computers is transparent to programmers. in another words, when programmers are developing parallel programs, they do n ' t need to learn any complicated primitives and write any codes related with communication between parallel tasks. just only set some parameters in the visual interfaces that provided by platform, and the codes will be generated by our system automatically and inserted to the fittest place in the files

    系統為每一個并行計算工程設定了一個基於master slave架構的并行編程模型，並且使得各結點機之間的通信對于開發人員透明化，也就是說，開發人員在開發并行程序時，無需了解紛繁復雜的通信原語，不涉及任務之間通信的代碼，只需要在并行程序開發平臺提供的可視化界面上對數據的傳送進行設定，通信代碼將自動生成並插入到程序合適的地方。
  3. Adsp sharc21060 is one of current digital signal processing boards based on super harvard architecture, and it " s architecture is designed to streamy parallel

    Adspsharc21060是一種基於超級哈佛結構的通用數字信號處理器， sharc的結構被設計為流水線并行處理器。
  4. On the other hand, boundary - scan technique intelligent fault diagnostic method was applied to practice. for most digital system, devices with boundary - scan architecture are broadly used. only using four line or five line to connect pc parallel port with cut tap ( test access port ), all the ptvs can be loaded to cut and all homologous prvs can be taken back to intelligent fault diagnosis system

    至於本文採用邊界掃描測試故障診斷技術，是考慮到本系統的通用性和簡潔性，因為對于大多數數字系統而言，具有邊界掃描結構的器件己廣泛應用，本文只需4條或5條信號線就能將pc機和被測邊界掃描電路連接起來，由此極大地簡化了智能故障診斷系統中為實現ptvs加載和prvs獲取而專門設計的介面板電路。
  5. Theebe - cg algorithm does not require construction of the global matrix. it can be implemented efficiently on a massively parallel architecture

    Ebe - cg演算法不需要構造全局矩陣，它在大規模并行結構中能被有效地實現。
  6. The cg algorithm does not require construction of the global matrix. it can be implemented efficiently on a abstract massively parallel architecture

    共軛梯度演算法不需要構造全局矩陣，它在大規模并行結構中能被有效地實現。
  7. According to characteristic of parallel mechanism and the different control rule between traditional nc machine and parallel nc machine, the cnc system with open modular architecture has been set up. because the software module and hardware module have been designed based on standardization and diversification, the deviser can set up system with different module such as building block

    根據並聯實驗平臺的結構特點以及它與傳統機床控制規律的不同，本文採用開放式、模塊化體系結構建造數控系統，在標準化與多樣化的基礎上設計了軟、硬體模塊，這樣就可以通過加減配置不同的模塊來構造數控系統，實現系統「積木式」的集成。
  8. Current work in progress is aimed at expanding the library with new protocol modules and a thorough investigation of parallel performance under the impact of different parallel architecture environment, node mobility as well as the suitability of optimistic synchronization algorithms

    當前工作的目的在於擴大新協議模型的庫，研究在不同并行體系結構環境影響下的并行性能，節點移動性和樂觀的并行演算法的適宜性。
  9. Three decoder architectures, parallel, serial and partially - parallel approaches, are analyzed in this thesis. a kind of novel partially - parallel architecture for decoding ldpc code is proposed. the trade - off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially - parallel architecture for the random parity check matrix

    論文分析了三種不同的譯碼器結構:并行結構、串列結構以及部分并行結構，並提出了一種新穎的部分并行結構的ldpc譯碼器，較好地解決了當校驗矩陣為隨機結構時，譯碼性能、硬體資源和數據吞吐量平衡的問題。
  10. This paper, first, studies the parallel architecture of np, and describe the chief design method and parallel processing technology of np from hardware and software, which gives the profile of np ’ s parallel architecture

    本文首先研究了網路處理器的并行體系結構。從硬體和軟體兩個方面綜述了現代網路處理器所使用的主要并行設計方法和并行處理模型。
  11. At the same time, this thesis has analyzed the programming method of parallel computing system based on network and optimized the original distributed architecture of surface vessel command and control system which is studied in this thesis according to parallelism, and provided a distributed network parallel architecture which is adapt to operational requirements of actual navy surface vessel command and control system, and discussed the feasibility and performance predominance of this kind of architecture

    同時，本文還深入分析了基於網路的并行計算系統程序設計方法，對本課題所研究的艦載指控系統原有的分散式體系結構按照并行化的思想進行了優化；提出了一種適合目前海軍艦載指控系統作戰要求的分散式網路并行體系結構；討論了這種體系結構的可行性和性能優勢。
  12. The distributed networked parallel architecture and load balance resolution scheme which is adapt to this kind of architecture have been simulated on the surface vessel command and control system artificial platform, and the experiment shows that the performance of the surface vessel command and control system is higher than that of the original distributed system by making use of this kind of method and proves that the method discussed in this thesis has some practical value

    本文所提出的分散式網路并行體系結構和適應于這種體系結構的負載平衡方法在艦載指控系統模擬平臺上做了模擬試驗，證明這種方法的應用使艦載指控系統在性能上比原有的分散式系統有所提高，從而驗證了本文所提出的方法具有一定的實用價值。
  13. In general, fpga is mostly used in high - speed communications systems or high - speed signal processing systems because of its high - speedly and parallel architecture. however, in this thesis, it was applied to a low - speed and low power consumption system - a underwater long - range remote control reception system to realize decoding of remote control instructions in the frequency domain, and made the satisfactory result

    一般來講， fpga多用於高速通信和高速信號處理領域，以發揮其處理速度快的特點，本文將其應用於一低速低功耗系統? ?某水下遠程遙控接收系統，主要用其在頻域來實現水下遠程遙控的解碼，取得了令人滿意的效果。
  14. So the egress of digital processing system lies in the parallel architecture

    因而其信號處理機的出路在於體系結構的并行化。
  15. So the egress of digital processing systern lies in the parallel architecture

    因而其信號處理機的出路在於體系結構的并行化。
  16. At last, it describes the scalable parallel architecture of advanced wp system based on multiple sharcs

    最後分析了基於多sharc的vvp可擴展并行處理系統的組成方式和結構特點。
  17. The thesis analyses the key technology of computer parallel architecture by constructing a system for dual - computer system parallel processing

    本文通過構建一個并行處理雙機系統分析了計算機并行系統的關鍵技術。
  18. According to the structure of quasi - cyclic ldpc code, we can make a trade - off between hardware complexity and decoding throughput by applying semi - parallel architecture

    摘要利用準循環ldpc碼的結構特點，使用半并行結構的譯碼器可以實現復雜度和譯碼速率的有效折中。
  19. Subsequently, a parallel architecture for the integer wavelet transform is present. and something about how the architecture works and some charts of this architecture are presented

    然後提出一種實現整數小波變換的并行結構，分析了該結構內部的工作流程，並給出了詳盡的原理圖。
  20. The video server with parallel architecture can extend the area of video service system, because it can disperse users " requests and reduce the local load of server and local traffic of networks

    採用并行服務器體系結構可以分散用戶請求、減輕服務器局部壓力和網路局部流量，擴大視頻應用的規模。
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