parallel register 中文意思是什麼

parallel register 解釋
並聯寄存器
  • parallel : adj 1 平行的;并行的 (to; with); 【電學】並聯的。2 同一方向的,同一目的的。3 相同的,同樣的,相...
  • register : n 1 記錄,注冊,登記,掛號。2 (人口動態,戶籍等的)登記簿,注冊簿;【商業】船籍登記簿;海關證明...
  1. The parallel number is applied to the shift register.

    并行數寄存於移位寄存器。
  2. The shift register is a device in which information may enter sequentially or in parallel.

    移位寄存器是一種能以串列和并行方式輸入信息的裝置。
  3. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載,和表明如果s1和s0為高電平,那麼它就不是連續輸入,在時鐘由低向高跳變后,在a端的數據輸入則在qa端輸出,在b端的數據輸入將在qb端輸出,等等。
  4. The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel

    以fpga ( fieldprogrammablegatearray )為控制核心,採用串列a / d變換器和通道隔離技術,實現了8通道并行採集和測試數據分時存儲功能,利用veriloghdl ( hardwaredescriptionlanguage )設計vxi寄存器基介面電路及各通道的控制電路。
  5. Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed

    採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re ( registerexchange )的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘,系統內部採用全并行的方式,以提供靈活的速度。
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