processing program processor 中文意思是什麼
processing program processor
解釋
處理程序-
In the thesis, based on design and implementation of the two signal processing system of different requirement, multi - dsp processor structure, dsp - pci interface, system control logic, pci device driver program, user application program are researched. the main content is list as follows : 1 ) according to the lfmcw radar signal processing algorithm, a signal processing system based on pc104 - plus bus is developed
本文通過對以上兩種雷達信號處理機的設計開發過程，研究了採用多片dsp信號處理器組建并行處理模塊實現信號處理演算法的方法，利用pci總線實現處理機數據傳輸介面，設備驅動程序和控制界面軟體開發，實現信號處理機數據傳輸控制等幾個方面的內容，主要工作如下: 1 ）針對線性調頻連續波雷達信號處理演算法，完成了基於pc104 - plus總線的嵌入式信號處理板的設計、製作以及調試。 -
This thesis deals with design and application of a multiprocessor made of four dsps in monitoring receiver. the broadband monitoring receiver requires a kind of chip with high performance because of complicated intermediate frequency signal processing. the author selects a kind of digital signal processor called adsp21160. during the process of design, the author uses cpld, fpga and some special cpus to finish signal, processing in the monitoring receiver. cluster multiprocessor based on vxibus made of four adsp21160 is put forward. the task distribution of four dsps is solved too. furthermore, data transition methods between chips at a high speed through link ports and chip extension mode using external port are recommended. the author debugs, emulates the program in one adsp - 21160 ez - kit lite and simulates the multiprocessor program in visualdsp + +
本文主要探討了監測接收機中多dsp處理模塊的設計與應用，寬帶監測接收機的中頻處理數據量大、實時性高，這樣，對dsp晶元提出了很高的要求，作者通過比較選擇了最適用於監測接收機的數字信號處理器adsp21160 ，並結合使用了cpld 、 fpga以及一些專用的cpu來完成監測接收機中的數據處理。作者提出了由四片adsp21160組成的簇式多dsp處理模塊的結構並配以了vxi總線，論述了簇式結構的特點，解決了多dsp處理模塊中四片adsp21160的任務分配問題。 -
With performance of up to 900 million floating - point operations per second ( mflops ) at a clock rate of 150 mhz, tms320c6711 is fit to tackle with the problem. this thesis made a deep research on the h. 263 standard and the tms320c6711. we propose the plan of the software and the hardware for the realization of the h. 263 protocol which include the structure of the whole program, the c code of the key algorithm of the h. 263, the c code of some subprogram, and the circuit for image processing with the tms320c6711 as the processor. furthermore, we optimize some subprogram in common use to make the coding more quickly. we encode a video sequence with the tms320c6711dsk successfully, even if the compression rate is as high as 100, video effect we get after decoding the code stream is satisfying
首先系統地研究了h . 263協議編碼器的基本演算法，句法，碼流結構和tms320c6711dsk的原理結構以及ccs2 . 0的開發環境；在系統的軟體方面給出了總體流程圖，對于h . 263協議編碼器的某些核心演算法和子程序，給出了部分源代碼，對于dsp的各種代碼優化方法進行了討論，並且對代碼進行優化，從而在提高系統處理速度的同時減少代碼大小和內存需求量；硬體方面以tms320c6711為核心處理器，提出了基於tms320c6711的圖像處理平臺的硬體實現方案，並給出了原理電路圖；最後在tms320c6711dsk上成功對視頻數據進行高壓縮比（ 100倍以上）的編碼，對回傳的結果解碼后得到了令人滿意的效果。
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