processor cache 中文意思是什麼

processor cache 解釋
處理器高速緩存
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  • cache : n. 1. （探險者等貯藏糧食、器材等的）暗窖，密藏處。2. 貯藏物。3. 【計算機】高速緩沖內存。vt. 1. 貯藏；密藏；窖藏。2. 【計算機】把…儲存到硬盤上。
  1. Operating system name and version, processor vendor model version speed cache size, number of processors, total physical memory, total virtual memory, devices, service type protocol port, and so forth

    操作系統名稱、版本號、處理器提供商/類型/版本/速率/緩存大小、處理器數量、物理內存總量、虛存總量、設備、服務類型/協議/埠號，等等。
  2. Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels. this paper present the architecture model of smpdca, and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi - ported cache

    Smpdca結構具有六個突出優勢：相對于大規模的超標量結構而言， smpdca結構的控制邏輯復雜性明顯要低得多；相對于通過共享主存來實現處理器之間的通信的結構而言，通過一個共享的第一級數據cache來實現處理器之間的通信的smpdca結構能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護開銷；數據cache命中率提高；便於smp （對稱多處理器結構）的軟體重用；從多個層次上開發程序的并行性。
  3. This kind of performance can match the speed of microprocessor bus operation. the size of a cache line is usually a few processor words

    由於cache的速度與cpu相當， cpu能在零等待狀態下迅速地實現數據存取。
  4. When a thread exits a synchronized block as part of releasing the associated monitor, the jmm requires that the local processor cache be flushed to main memory

    當線程為釋放相關監視器而退出一個同步塊時， jmm要求本地處理器緩沖刷新到主存中。
  5. Fields would be made directly to main memory, instead of to registers or the local processor cache, and that actions on volatile variables on behalf of a thread are performed in the order that the thread requested

    欄位的讀寫直接在主存而不是寄存器或者本地處理器緩存中進行，並且代表線程對volatile變量進行的這些操作是按線程要求的順序進行的。
  6. The processor accesses the cache before accessing the main memory

    處理器在存取主要的記憶之前存取隱藏所。
  7. If the processor reads a cache, a search is made to determine if the target is in the cache

    如果目標是在隱藏所中，如果處理器讀一個隱藏所，搜尋被做決定。
  8. This rack - mount system features four intel itanium 2 processors running at 1. 5 ghz. each processor has 6mb of l3 cache. the chipset is the intel e8870 server chipset

    這個機架式系統具有四個運行頻率為1 . 5ghz的intel itanium 2處理器，每個處理器都帶有6mb的三級緩存，其晶元組為intel e8870服務器晶元組。
  9. 3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies. to improve cache performance under sma model, the paper introduces hardware software co - operative optimization

    3針對多線程模式下訪存負荷加重的問題，為sma模型設計了軟硬體協同預取機制，並為sma模型設計了cachefilter來消減無效預取。
  10. As there are other processor measures such as size of a chip cache, speed of memory bus, and word width, there are at least three other noteworthy measures of beowulf performance

    正如其它度量處理器的手段有晶元緩存的大小、內存總線的速度和字寬一樣，至少有三種值得注意的度量beowulf性能的方法。
  11. And described three ways in detail separately : more access ports and non - blocking cache and quick hit buffer ( qhb ), and analyzed their performance. smpdca is a promising processor architecture

    並分別對更多的訪問埠、非阻塞cache以及快速命中緩沖區（ qhb ）等三種方法進行了詳細描述和性能模擬分析。
  12. A process thread can migrate from processor to processor, with each migration reloading the processor cache

    進程線程可以在處理器間遷移，每次遷移都重新加載處理器緩存。
  13. Property. a process thread can migrate from processor to processor, with each migration reloading the processor cache

    進程線程可以在處理器間遷移，每次遷移都重新加載處理器緩存。
  14. Bbl back - side bus logic. logic for interface to the back - side bus for accesses to the internal unified level two processor cache

    後端總線邏輯。訪問內部統一二級處理器緩存的後端總線介面邏輯。
  15. The value is the latest written by any processor in a computer, regardless of the number of processors or the state of processor cache

    無論處理器的數目或處理器緩存的狀態如何，該值都是由計算機的任何處理器寫入的最新值。
  16. In windows 2000 and later, a thread in a process can migrate from processor to processor, with each migration reloading the processor cache

    在windows 2000及更高版本中，進程中的線程可以在處理器間遷移，每次遷移都重新加載處理器緩存。
  17. Specifying a processor for a thread can improve performance under heavy system loads by reducing the number of times the processor cache is reloaded

    在系統負荷繁重的情況下，為線程指定處理器可以減少重新加載處理器緩存的次數，從而提高性能。
  18. Under heavy system loads, specifying which processor should run a specific thread can improve performance by reducing the number of times the processor cache is reloaded

    在系統負荷繁重的情況下，指定哪個處理器運行特定的線程可以減少重新加載處理器緩存的次數，從而提高性能。
  19. Based on investigations of memory access behavior, through experimentations of spec cpu2000 benchmarks running on godson - 2 processor, several policies that can improve performance of cache and memory system significantly are proposed and evaluated in this dissertation. the proposed techniques can increase memory access bandwidth while decrease access latency so that ipc of the processor is increased

    本文從提高處理器的ipc值和優化處理器的訪存延時及帶寬的角度出發，結合分析龍芯2號處理器運行speccpu2000測試程序的訪存行為特徵，對存儲系統性能優化技術進行研究，提出了一系列存儲系統的性能優化技術並對所提出的優化技術進行性能評測與分析。
  20. Creating user controls to cache content allows you to separate portions of a page that take valuable processor time to create, such as database queries, from other parts of the page

    通過創建用戶控制項來緩存內容，可以將頁上需要花費寶貴的處理器時間來創建的某些部分（例如數據庫查詢）與頁的其他部分分離開。
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