processor bus 中文意思是什麼

processor bus 解釋
處理機總線
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  1. To carry out a fetch, the processor place ( enables ) the binary - coded address of the desired location onto the address line of the external processor bus

    為了完成一個取數操作，處理器將所需的單元的二進制編碼的地址放（使能）在外部處理器的地址線上。
  2. The development of fieldbus technology made lonworks field bus outstanding in all kinds of fieldbus. this paper simply introduces some kinds of common using fieldbus and the important position and influence of lonworks fieldbus in all kinds of fieldbus, carefully describes the technology core of lonworks technology, puts great emphasis on the introduction of the development and design of public security node of intelligent district which adopts computer, communication and control technology, carefully designs the interfaces of hardware circuits. the public security node of intelligent adopts 8031 single chip as its main processor to complete the application program of user, which mainly collects, process and control all kinds of field signal, and neuron chip 3150 as its slave processor to communicate with other nodes on field network, which works under parrel slave a mode

    現場總線技術的發展使得lonworks技術脫穎而出，本文簡要介紹了常用的幾種現場總線的概況以及lonworks技術在現場總線技術中的地位和影響，對lonworks技術的技術核心：神經元晶元、 lontalk協議、 lonworks收發器、 lonbuilder及nodebuilder進行詳盡的描述；重點介紹了集先進的計算機技術、通信技術、控制技術為一體的智能小區安防節點的開發與研製，對節點硬體電路的各種介面進行了詳盡的設計。本文設計的智能小區安防節點採用單片機8031作為主處理器來完成用戶的應用程序，主要負責對各種現場信號進行採集、處理及控制，工作在并行從a方式下的神經元晶元mc3150作為從處理器，主要完成與現場網路上的各節點及中心控制室之間的通信工作。
  3. The characteristics and the design concepts of the transient electro - magnetic methods system design of predecessors will be analyzed detailedly in this thesis, on the foundation, the transient electromagnetic exploration system based on dsp ( digital signal processor ) and usb ( universal serial bus ) was designed, in which the transmitter and receiver have been integrated together for the sake of better operation for exploration

    在總結前人在系統設計的基礎上，成功設計和實現了一套基於dsp （ digitalsignalprocessor ）和usb （ universalserialbus ）技術的瞬變電磁探測系統，本論文就該系統的設計思想和原理進行了詳細論述和分析。
  4. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。
  5. Tms320vc5402 is a fixed - point digital signal processor, made by texas instruments incorporated, which is 16 - bit word length. vc5402 has enhanced harvard architecture built around one program bus, three data buses, and four address buses for increased performance and versatility

    另外，採用mcs - 51系列cpu作為採集處理卡板載mcu也存在一些比較嚴重的問題，如cpu的指令執行速度慢，總線帶寬窄等缺點，不能完成數據的高速處理。
  6. As the requirements of its function, a bus control interface board has already been designed. also the paper have provided the scenarios demonstration for the bus control interface board ( bcib ), the design for the protocol of communication, the hardware for bcib, the software for bcib, and the software for the processor ' s communication. while the analysis for the capability of real - time and the calibration and test for subsystem have been also finished. during the design, the system advanced ability, reliability, resources availability and the cost - efficency ratio are considered. the issus such as system integrated control, mutual exclusion of the shared storages, generation of handshaking signal and system self - test were resolved

    本論文主要對航空自衛系統的綜合化方式進行了深入研究，並按其功能等方面要求，對航空自衛系統綜合化總線通信模塊進行了設計，主要完成了總線通信模塊方案論證、通訊協議設計、總線通信模塊硬體設計、總線通信模塊（ bcib ）軟體設計、處理機通信軟體設計、實時性分析、系統調試、試驗等項工作，在設計過程中，綜合考慮了系統先進性、資源利用率、費效比及可靠性等因素；重點解決了系統綜合控制方式、共享存儲器互斥、握手信號產生及系統自檢測等問題。
  7. Aim at the dtc ' s blemish mentioned above and the direction of dtc technique development, the dissertation put great emphasis on the work as follows, with an eye to exalt dtc system function : ( 1 ) a new speed - flux observer of an induction motor is proposed to enhance the accuracy of flux observing, which is an adaptive closed - loop flux observer and different from the traditions. a new adaptive speed - observation - way is deduced out according to the popov ' s stability theories ; ( 2 ) to improve the performance of dtc at low speed operation, we have to exalt the accuracy of the stator flux estimation and a new way of bp neural network based on extended pidbp algorithm is given to estimate and tune the stator resistance of an induction motor to increase the accuracy of the stator flux estimation ; ( 3 ) digital signal processor is adopted to realize digital control. an device of direct torque control system is designed for experiment using tms320lf2407 chip produced by ti company ; ( 4 ) bring up a distributed direct torque control system based on sercos bus, sercos stand for serial real time communication system agreement which is most in keeping with synchronous with moderate motor control ; ( 5 ) the basic design frame of the hardware and software of the whole control system is given here and some concrete problem in the experiments is described here in detail

    針對上面提到的直接轉矩控制的缺陷和未來直接轉矩控制技術發展方向，本論文重點做了以下幾個方面的工作，目的在於提高dtc系統的綜合性能： （ 1 ）提出一種新型的速度磁鏈觀測器，新型的速度磁鏈觀測器採用自適應閉環磁鏈觀測器代替傳統的積分器從而提高磁鏈觀測的精度，並且根據popov超穩定性理論推導出轉速的新型自適應收斂律； （ 2 ）改善系統的低速運行性能，主要從提高低速時對定子磁鏈的估計精度入手，提出了一種提高定子磁鏈觀測精度的新思路? ?利用基於bp網路增廣pidbp學習演算法來實時在線地修正定子電阻參數； （ 3 ）採用數字信號處理器dsp實現系統全數字化硬體控制，結合ti公司生產的tms320lf2407晶元，設計了直接轉矩控制系統的實驗裝置； （ 4 ）提出了基於sercos總線網路化分散式的直接轉矩控制系統， sercos （ serialrealtimecommunicationsystem ）是目前最適合同步和協調控制的串列實時通信協議； （ 5 ）基本勾勒出整個控制系統的硬體和軟體設計基本框架，詳細描述一些實驗中的具體的細節問題。
  8. In the thesis, based on design and implementation of the two signal processing system of different requirement, multi - dsp processor structure, dsp - pci interface, system control logic, pci device driver program, user application program are researched. the main content is list as follows : 1 ) according to the lfmcw radar signal processing algorithm, a signal processing system based on pc104 - plus bus is developed

    本文通過對以上兩種雷達信號處理機的設計開發過程，研究了採用多片dsp信號處理器組建并行處理模塊實現信號處理演算法的方法，利用pci總線實現處理機數據傳輸介面，設備驅動程序和控制界面軟體開發，實現信號處理機數據傳輸控制等幾個方面的內容，主要工作如下: 1 ）針對線性調頻連續波雷達信號處理演算法，完成了基於pc104 - plus總線的嵌入式信號處理板的設計、製作以及調試。
  9. This kind of performance can match the speed of microprocessor bus operation. the size of a cache line is usually a few processor words

    由於cache的速度與cpu相當， cpu能在零等待狀態下迅速地實現數據存取。
  10. Measure and control unit adopted 16 - bit, high - speed a / d converter, it can guarantee the speed and precision of alternating sample. the part of communication adopted can bus to transmit the data, it was suitable for real - time control and can guarantee dependability. it adopted the can bus adapter of yan - hua company whose type was pcl - 841 to communicate with processor unit the processor unit adopted industrial pc, which can guarantee the system work well for a long time

    其中下位裝置採用西門子公司的高性能十六位處理器c167cr - lm ，其內嵌can總線控制器便於通過can總線與上位機進行通訊，數據採集部分採用十六位高速a d轉換器從而保證了交流采樣的速度與精度，通訊部分採用可靠性高，適于現場實時控制的can總線來傳輸數據，與上位機介面採用研華公司的型號為pcl - 841的can總線適配器，為保證系統長時間可靠運行上位機採用工控機。
  11. The main outline included the specification of enhancement processor 1c and pci bus, how to generate the system control signals and achieve transmission complied with pci bus specification by use of fpga design

    討論了最新視頻逐行處理專用晶元的使用和配置、 pci總線規范以及如何用fpga實現系統控制信號和模擬實現pci總線傳輸。
  12. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  13. The designed bus controller performs perfectly in the phase of system test. especailly, the communication between bc and psp ( power system processor ) is very successful

    所設計的匯流條控制器功能完善、性能穩定，並實現了與電源系統處理機的聯調，達到了預期的設計目的。
  14. Specification for processor system bus interface eurobus a

    處理器系統總線介面
  15. A information processing - processor system bus interface eurobus a

    信息處理處理機系統總線介面
  16. This paper deals with implementing, by the virtual vxi - bus system, the dynamic testing equipment of the processor of the intake channel control system of airplanes. it also studies integrating the vxi - bus based testing system with the hardware modules and programmed the associated application software

    本文通過應用vxi總線虛擬儀器技術實現對飛機進氣道控制系統處理機動態測試設備的研製工作，對vxi總線測試系統的集成進行了研究，並編寫了應用軟體。
  17. It starts with a concise introduction of the concept of virtual instrumentation and vxi bus " structure, and then, oriented toward developing a testing system for the dynamic testing equipment of the processor of the intake channel control system of airplanes, this paper presents the ideas of a vxi bus - based testing system, its structure and hardware / software design. the testing software, which cooperates with the hardware to fulfill the testing functions, is programmed with labview ( a virtual instrumentation development platform )

    論文在簡要介紹虛擬儀器的概念以及vxi總線系統的結構、特點的基礎上，結合飛機進氣道控制系統處理機動態測試設備的研製，闡述了基於vxi總線的測試系統的測試思想、總體結構和硬、軟體設計；並利用labview （虛擬儀器的軟體開發平臺之一）編制了飛機進氣道控制系統動態測試設備的測試軟體，該軟體配合硬體系統完成動態測試設備的各項功能測試。
  18. The high contention rate of the processor bus becomes a performance bottleneck

    對處理器總線的高爭奪率成為性能瓶項。
  19. The numa architecture can increase processor speed without increasing the load on the processor bus

    Numa體系結構可以在不增加處理器總線負載的情況下提高處理器速度。
  20. The internal processor bus described in sec. xx is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit

    Xx節所描述的內部總線通過一組位於微處理器集成電路內的總線緩沖器與外部總線連接。
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