processor interface module 中文意思是什麼
processor interface module
解釋
處理機介面模件-
Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method
在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。 -
After that, based on the datum of the dsp and the correlative chips, the paper designed the key circuit in the data processor module. the design of the interface modules of the control system is the following work. they were the interfaces connecting controller with digital, analog network, and the monitor computer respectively
接下來，設計了系統的整體結構；研究分析了嵌入式控制系統在進行數據處理時所採用的器件以及dsp和相關的晶元資料之後，確定使用tms320vc5402作為系統的數據處理器，設計了數據處理模塊的部分關鍵電路和dsp的16位並口自舉加載方式。 -
The task in the paper comprises two parts. the software design procedure works as follow, program the drivers for module on pc with cvi, generate the corresponding ddl and then edit the test serial and invoke the ddl by designing soft panel with vc + + 6. 0. thus facilitate users to control module to conduct high speed data test. the hardware design procedure works as follow, design vxi message based interface circuit and plesio - fdc circuit with fast data transport function on xc2vp30, a virtex - ii pro series fpga chip designed by xilinx company which integrates power - pc processor
筆者負責的工作包括軟體設計和硬體設計兩部分:軟體設計是用cvi工具編寫模塊在pc機上的驅動程序，生成動態連接庫，再用visualc + + 6 . 0設計軟面板，實現測試矢量的編輯和動態連接庫的調用，讓用戶很方便地控制模塊進行高速數據測試;硬體設計是在xilinx公司的一片集成了power - pc處理器的virtex - iipro系列fpga晶元xc2vp30上完成vxi總線的消息基介面電路設計和具有快速數據傳送功能的準fdc電路[ 1 ] [ 2 ]設計。 -
In the first step, the author introduces the rtxc real time operation system and illustrate in detail the boot code design of arm processor, secondly, the author offers a whole structure under this operation system and explains the function of this software in terms of four relative tasks, in which the signal processing module, interface interrupt processing module, system operation measuring and controlling module and rc & lc information processing module are illustrated at length
先介紹了實時操作系統rtxc ，詳細闡述了arm處理器啟動代碼程序的設計，然後給出了在此操作系統下軟體設計的整體結構，分四個任務分別闡述此軟體功能，其中詳細介紹了信令處理模塊、介面中斷處理模塊、系統運行監測模塊和rc消息lc消息處理模塊。 -
Deep discussions are offered for design and realization of several key technology, such as serial communications bsp design and realization, frame relay protocol design and realization, design and realization of interface between vxworks rtos and char & network devices, and powerpc860 ' s communications processor module
對很多設計與實現中的關鍵技術，如串列通訊bsp的設計與實現、幀中繼協議的設計與實現、 vxworks嵌入式實時操作系統與字元設備和網路設備的介面方式的設計與實現、以及powerpc860處理器中的通訊處理器模塊（ cpm ）進行了較為深入的討論。 -
Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition
Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。 -
On account of actual demand, an ip core of 32bits / 33mhz pci interface module based on fpga has been designed by virtue of vhdl, and the 32 bits microblaze processor soft core has been embedded into this fpga. so, a fast and highly efficient pci master / slave interface, a local processor and other control logic are integrated on one chip of fpga
根據實際需求，利用vhdl硬體描述語言設計了基於fpga的32位/ 33mhz的pci介面模塊的ip核，並內嵌xilinx公司的32位軟處理器核microblaze ，從而在一片fpga上就實現了快速高效的pci主從介面和本地端處理器及其他控制邏輯。 -
In this paper, with the help of the idea of software engineering, the object - oriented developing technique, structured software development method, the inter - process communications in windows and the fortran / c + + mixed programming technique, the windows version of the pre - processor and the post - processor module are developed : the pre - process module is parted as four function modules. the part of graphic display codes of the pre - processor and the post - processor module are translated and modified as background processes. the interactive graphic interface in windows style is designed as foreground processes
基於軟體工程思想，本文綜合運用面向對象技術、結構化程序設計方法、 windows進程間通信技術、 fortran c + +混合聯編技術，對sheet - forming的微機版本中的前、后處理器模塊進行了研製：將前處理器模塊進一步劃分為四個功能模塊；優化編譯前、后處理器的圖形顯示部分代碼並將其作為后臺程序；設計windows風格的前臺互動式圖形界面；利用本文設計的中介程序實現后處理前臺界面和后臺程序之間的通信。 -
This paper projects a utility subdividing drive system of step motor, which consists of digital control module, drive module and power module, it uses at89c52 single chip processor as the core, it realizes the external event or generates control signal by i / o interface, timer and external interruption, the system introduce pld device and isp technology to the design of phase sequencer, it simplified circuit and improved the anti - disturbing capability by using abel - hdl language, this system can realizes data memory, velocity digital control and led display, etc. this paper adopted firstly the single - chip technique to design control system, which replaced old complicated logic control circuit and simplified test process
本文研究了一種實用的步進電機細分驅動系統，由數字控制模塊、驅動模塊和電源模塊組成，系統以at89c52單片機為核心，通過單片機的i o口、定時器計數器中斷來實現外部事件監控以及控制信號的產生，系統將可編程邏輯器件（ pld ）器件和在系統編程（ isp ）新技術引入到細分驅動環行分配器的設計，通過abel _ hdl語言編程實現硬體軟化設計和邏輯重構，大大簡化了電路，並提高了電路抗干擾能力。使系統實現參數存儲，速度數字控制，數碼顯示，進退刀控制等功能。 -
The software and hardware design of smart card interface module of system on a chip based on mips processor is discussed in this dissertation
本文主要討論基於mips處理器的片上系統的智能卡介面模塊的軟、硬體設計。 -
I have studied the designing technique of the interface circuit in the course of designing entirely, have put forward the interface model with the processor and system controller of the base in wireless communication ; design data line up with data interface, line up module propose horizontal input, vertical algorithm that output in data
筆者在整個設計過程中，研究了介面電路的設計技術，提出了無線通信中基帶處理器與系統控制器的介面模型；設計了數據排隊與數據介面，在數據排隊模塊提出了橫向輸入、縱向輸出的演算法。
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