simulation gate 中文意思是什麼
simulation gate
解釋
模擬門- simulation : n. 假裝；模擬；裝病，裝瘋；【生物學】擬態，擬色。
- gate : n 1 大門，扉，籬笆門，門扇。2 閘門；城門；洞門；隘口，峽道。3 【冶金】澆注道，澆口，切口；【無線...
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Modeling and simulation of hydraulic system of water gate using the distributed physical net modeling approach
閘門液壓系統分散式物理圖網建模及模擬研究 -
Numerical simulation research to the coal pillar leaving under different mining condition in air gate of lin huan coal mine
臨渙礦風巷不同采動條件煤柱留設數值模擬研究 -
The operation of the simulation model showed that it is completely feasible to study the dynamic behavior of the pneumatic flap gate system of dry docks by using the described model
通過對模擬模型的運行表明：用所述的模擬模型研究干船塢氣控臥倒塢門系統的動態特性是完全可行的。 -
To understand better the dynamic behavior of pneumatic flap gate of dry docks so as to shorten the design period of the dock gate and cut down the cost of tests, a kinetic simulation model for the pneumatic flap gate system of dry docks has been established by using adams - automatic analysis software for the dynamics of a mechanical system
摘要深入了解干船塢氣控臥倒門系統的動態特性，以便縮短塢門的設計周期，節約試驗費用；運用機械繫統動力學自動分析軟體adams ，建立了干船塢氣控臥倒門系統的動力學模擬模型。 -
After that, the system and function simulation platform are introduced, and the simulation results are analysed. moreover the gate - level simulation is done after the ip code is synthesized
之後，介紹了此ip核的系統模擬平臺和功能模擬平臺，並對端點0的各個邏輯功能塊的功能模擬的結果進行了分析。 -
Speed - up techniques for gate - level power estimation are proposed. an efficient power estimation flow is presented firstly to reduce the power simulation time
本文的主要貢獻如下: 1 .提出了加速門級功耗模擬與分析的方法。 -
Abstract : a new approach, gate - capacitance - shift ( gcs ) approach, is described for compact modeling. this approach is piecewise for various physical effects and comprises the gate - bias - dependent nature of corrections in the nanoscale regime. additionally, an approximate - analytical solution to the quantum mechanical ( qm ) effects in polysilicon ( poly ) - gates is obtained based on the density gradient model. it is then combined with the gcs approach to develop a compact model for these effects. the model results tally well with numerical simulation. both the model results and simulation results indicate that the qm effects in poly - gates of nanoscale mosfets are non - negligible and have an opposite influence on the device characteristics as the poly - depletion ( pd ) effects do
文摘:提出了一種新的建立集約模型的方法，即柵電容修正法.此方法考慮了新型效應對柵電壓的依賴關系，且可以對各種效應相對獨立地建模並分別嵌入模型中.另外，利用該方法和密度梯度模型建立了一個多晶區內量子效應的集約模型.該模型與數值模擬結果吻合.模型結果和模擬結果均表明，多晶區內的量子效應不可忽略，且它對器件特性的影響與多晶耗盡效應相反 -
By analyzing the features of metro entry gate ( eng ) queuing system, a computer simulation model is established
摘要通過對城市軌道交通進站檢票機排隊系統特徵的分析，建立了進站檢票機模擬系統。 -
The authors argon list the computer simulation method optimizes the scheme of metro eng, and thus can offer the basis of determining the metro gate number for the design and operation departments of urban rail transit
提出的優化車站檢票機配置的計算機模擬方法，可以為城市軌道交通設計、運營部門在確定車站檢票機配置數量時提供決策依據。 -
Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大 -
It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。 -
Sorting algorithm can solve logic gate circuit for more fanout, more loop nestification and feedback alternately. we sort these nodes according to their joint relationship by the sort algorithm that can determine the priority order of digital circuit simulation and give the feedback chain
排序演算法可以解決具有多扇出、多迴路嵌套及交叉反饋的邏輯門電路，按照其連接關系進行排序，並給出其中的最大反饋鏈。 -
Once again using moldflow injection molding simulation software, engineers analyze how a part should be molded accounting for gate locations, wall thicknesses, size, and type of material
根據澆口位置、壁厚、零件大小和注塑材料的種類，使用注塑模擬軟體，分析零件應該怎麼樣模塑。 -
By means of the integration of numerical simulation methodology and optimization algorithms, a new method for the optimization of gate location by experiential scouting was put forward
摘要將數值模擬技術和優化演算法相結合，提出了基於數值模擬技術的澆口位置的優化方法：經驗搜索法。 -
The whole circuit consists of a multiplier, an error amplifier, a comparator, a rs flip - flop, an and gate, and an inverter, etc. the electronic circuit simulator cadence is utilized to practice the detailed functional simulation of the general circuit and the subsystem circuits
整個電路由模擬乘法器、誤差放大器、比較器、 rs觸發器、與門和倒相器等基本單元電路組成，採用工作站上的大型ic設計軟體cadence進行模擬。 -
The test bench program is a virtual pci system, which comprise the microblaze model established from xilinx edk and also the pci / pci - x model from synopsys company. function level or gate level simulation can be done on this test bench
測試平臺中，利用xilinxedk生成的microbalze處理器模擬模型，以及synopsyspci / pci - xflexmodels模型組建了一個虛擬的pci系統，可進行門級和行為級的模擬。 -
Numerical simulation of energy dissipator with new style flaring gate pier and stepped spillway
新型寬尾墩和階梯式溢流壩面一體化消能工數值模擬 -
Then the simulation tests on drum excess water and lack of water were practiced ; the results indicate that : if the network parameters are selected correctly ， the training samples can be convergent to a relative small and stable value with a small learning error. some comparisons can be made through sample training under the circumstance of me and the hme, after adopting hme with the tree - style structure, two layers of the gate network can enhance the control of the algorithm system. as a result the precision and stability is improved
其實驗結果表明：只要合理選取網路參數，本文所編輯的樣本均能收斂於一個較小的穩定值，訓練誤差也較小，並且通過分層與不分層混合專家網路的樣本訓練結果比較可知，採用這個具有樹結構型式的分層混合專家網路，由於其中兩層門網路對系統的控製作用加強，因此樣本訓練的精度與穩定性有所提高。 -
Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired
在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。 -
And the process of functional verification consists of the implementation of rtl ( register transfer level ) simulation, gate level simulation and post - layout simulation in the process of design
驗證最關鍵的是測試方案的制定，而功能驗證的過程是在於在設計過程中實施rtl級模擬、門級模擬和后模擬。
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