timing and control circuit 中文意思是什麼

timing and control circuit 解釋
定時及控制電路
  • timing : n. 1. 時間選擇。2. 定時,校時,計時,調速。3. 【自動化】同步;時限。
  • and : n. 1. 附加條件。2. 〈常 pl. 〉附加細節。
  • control : n 1 支配,管理,管制,統制,控制;監督。2 抑制(力);壓制,節制,拘束;【農業】防治。3 檢查;核...
  • circuit : n 1 (某一范圍的)周邊一圈;巡迴,周遊;巡迴路線[區域];迂路。2 巡迴審判(區);巡迴律師會。3 【...
  1. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表,而是由產生基準頻率的信號發生器(如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等)中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備,它提供用在通信系統中控制某些功能的定時的時間基準設備,時鐘提供的信號稱為基準信號、定時信號或同步信號。
  2. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成,實現了任意窗口尋址等復雜指令操作,將整個處理器的數據通路與控制通路分離,減小了電路時延,從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求,構成了統一的、緊密聯系的、協調的md32系統結構。
  3. This paper briefly introduces design method of the multi - function timing control unit. it is made of 89c51 and other integrate circuit chip, and produce the frame diagram for monitoring program

    摘要介紹了一種多功能定時控制器的設計方法。它是由89c51單片機和幾個主要的集成電路晶元構成。並給出了監控軟體的結構框圖。
  4. This paper explains the bluetooth technology in detail, and designs the circuit and arithmetic of package composing, data error detection and correction, data whitening, receive / transmit routines, traffic control, receive / transmit timing, channel control and hop selection

    為了驗證本系統的性能,本論文應用模擬工具對穩定通信條件下的系統和一般直擴通信系統作出模擬,經過對誤碼性能的對比,得出本系統優於一般直擴系統,具有良好的性能。
  5. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中,重點介紹了語音的輸入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等,並且給出了在硬體電路設計和調試過程中的問題與解決辦法。
  6. In this paper, the digital image real - time processing system was a very important part of fed driving circuit system. altera fpga chip was used to complete operation on reading and writing and timing control of fed image data. the image process algorithms mainly used gray - level transformation in the theory of image enhancement, and the algorithm realized luminance non - uniformity control, gray - level non - linear correction and automatic power control for fed

    本文設計的基於fpga技術的數字圖像實時處理系統是fed驅動系統中的重要組成部分,其核心部分採用了altera公司的fpga晶元,實現對fed圖像數據讀、寫操作和時序控制等,而圖像處理的演算法部分主要是利用圖像增強技術理論中的灰度變換方法,實現對fed的亮度非均勻性控制、灰度非線性校正以及fed的自動功率控制。
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