verification stage 中文意思是什麼

verification stage 解釋
論證期
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  • stage : n 1 講臺；舞臺；戲院，劇場；〈the stage〉戲劇，戲劇藝術；戲劇文學；〈the stage〉戲劇業；劇壇。2 ...
  1. This exception is thrown during the verification stage of the linking phase of class loading

    這個異常是在類別載入的連結階段的校驗過程中拋出。
  2. ( 3 ) smg model is not only good at practicability but also information ability due to real time updating, which guarantees the precision of the model forecasts. and no matter what stage is, calibration or verification, and what kinds of runoff situation, most plentiful runoff or most shortage, very close forecast precision in each case is obtained

    （ 3 ） smg模型不但實用而且可以進行實時的修正，使其預報精度能夠得到較好的保證，且不論在率定期、還是在檢驗期、不論對特豐徑流預報，還是對特枯徑流預報，他們的精度都比較接近，說明模型具有一定的泛化性。
  3. On the stage of review and prosecution, people ' s procuratorate shall offer convenience for the lawyer who undertakes legal aid of the case to consult extract and duplicate the judicial documents pertaining to the current case and the technical verification material

    十五、在審查起訴階段，人民檢察院應當為承辦法律援助案件的律師查閱、摘抄、復制案件的訴訟文書、技術性鑒定材料提供便利條件。
  4. ( 4 ) both multi regression model and generalized tank model have high precision in calibration stage, but sharply decrease in verification. beside that, the quantity of observed data is vital for these two models. so it is suggest that the models be not adopted when data sequence is less than 12 years

    西安理工大學碩士學位論文（ 4 ）多元回歸模型和概化的水箱模型，在建模時精度較高，檢驗時下滑，而且對資料系列長度的要求比其它模型要多得多，在資料不足12年的情況，建議不要使用這兩個模型。
  5. Simulation technology shall be utilized to simulate the real running of embedded hardware system to enable the software development and system integration implemented on a virtual stage, so as to complete the system model verification and running activity analysis before the manufacture of hardware prototype, avoiding the mutual wait between the software development and hardware development, in order to improve the development efficiency and lower the risks and costs

    利用模擬技術模擬嵌入式硬體系統的真實運行，使軟體開發和系統集成在虛擬平臺上進行，在硬體原型製造前就完成系統模型驗證和運行行為分析，避免軟硬體開發相互等待，提高開發效率，降低風險和成本。
  6. Recently, embedded software simulation development environment has been used widely, it shall be utilized to simulate the hardware system to enable the software development and system integration implemented on a virtual stage, so as to complete the system model verification and running activity analysis before the manufacture of hardware prototype

    利用軟體技術模擬嵌入式硬體系統的真實運行，在模擬平臺上進行嵌入式軟體的開發和系統集成。在硬體原型製造前就能夠完成系統模型驗證和運行行為分析，避免軟硬體開發相互等待，從而降低了成本，提高了開發效率和競爭力。
  7. Then we do some research about the basic protocols, the elliptic curve diffie - hellman protocol is improved as it can ’ t make identity authentity and can ’ t resist third party ’ s attacks ; at the same time, the signature equation of elliptic curve digital signature algorithm is reconstructed, and the improved kp + lqalgorithm is applied into verification stage, the whole speech of the protocol is improved greatly

    接著，研究和分析了基於ecc的各類密碼協議。針對密鑰交換協議不能進行身份鑒別以及存在第三方攻擊的問題，對其加以改進;同時，對數字簽名協議中的簽名方程重新構造，並將優化的kp + lq演算法用於驗證過程，提高了協議的執行效率。
  8. How to reduce noise figure of operational amplifier are studied in this paper. through design of a low - noise opa, introduce low - noise design of the input stage in detail. and with the analysis of computer, suitable sizes of the input apparatus are choosed. at last, by simmulation and verification on this opa, the result is satisfied

    研究了如何從電路結構上減少運算放大器的噪聲，以一種低噪聲運放為例，著重介紹輸入級設計，並藉助計算機分析選擇合適的輸入器件尺寸，最後通過對運放噪聲的模擬驗證，得到了滿意的結果。
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