vlsi level 中文意思是什麼
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It must be appreciated and accepted in telecom market, due to its advanced technology reliable performance and high cost performance. a series of technical key problems have been solved, mainly f an overal exhaustive design of the 128k switching network system was presented based on 4k net - chips, with our own intellectual property a 3 level 64k switching net was successfully designed, in which the tlevel consists of l6 4k net - chips and the s - level consists of a self designed single vlsi fpga chip with 560 pins. an optical net interface and an optical multiplexer were designed to carry out the voice transmission and distribution of l28, 000 users
在研究開發過程中，解決了一系列的技術關鍵問題，主要有：提出了基於有自主知識產權的4k網片的128k網路系統的總體設計方案；研究設計了tst三級結構64k交換網，其中t級含有16片4k網片， s級由自行設計的、 560pins的、單片大規模fpga實現；研究設計了雙機雙網雙余度的通信控制處理器系統，實現了對用戶呼叫、 tst各級網路的控制、報警等各種功能；研究設計了光網介面oni和光復用器omux ，實現了12 . 8萬用戶話音的傳輸分配。 -
This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design
本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。 -
As the technological level of lsi and vlsi steadily development, the scale and the complexity of digital system are expanded at very high speed
隨著lsi和vlsi工藝水平的不斷發展，數字系統的規模和復雜性正以前所未有的速度不斷擴大。 -
Vlsi systems, 1998, 6 : 58 - 66. 24 kim k, karri r, potkonjak m. configurable space processors : a new approach to system - level fault tolerance. in proc
為了解決這一問題，本文又提出了一種新的使用互補邏輯-交替互補邏輯cl - acl切換模式的dmr結構文中稱之為cl - acl結構。 -
The fast development of vlsi technology has provided the base of hardware for fpga ( field programmable gate array ) is most suitable for performing real - time pixel - level image processing operations
Vlsi技術的迅猛發展為數字圖像實時處理技術提供了硬體基礎。其中fpga （現場可編程門陣列）的特點使其非常適用於進行一些基於像素級的圖像處理。 -
From the view point of the foundation of dft ( which includes the testable measure of gate - level circuits, the testable and controllable measure of functional - level, the flow and methodology of dft and so on ), the author introduce some common testing technology such as scan and bist in modern times. especially the boundary scan technology has been widely adopted in the dft of vlsi. with the special controller, the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports, and the response could also be shifted to the testing output ports
本文從可測性設計的基礎理論出發（包括門級電路的可測性測度、功能級上的可測性和可控性、可測性設計的流程和方法等） ，介紹了現代常用的可測性技術，比如：掃描技術、內嵌自測試技術等，特別是邊緣掃描技術已經廣泛地應用到vlsi的可測性設計之中，它通過特定的控制器，從相應的測試輸入埠將測試向量掃描至芯核所對應的管腳，再將結果從相應的測試輸出埠掃出。 -
Low power vlsi designs can be achieved at various design levels, which rang from circuit, logic, architecture and algorithmic ( behavioral ) levels to system level, according to the down - top design flow
超大規模集成電路低功耗設計可以在不同的設計層次進行考慮，自下而上分可以分為：物理層、邏輯層、結構層、演算法（行為）層和系統層。
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