指令執行速率 的英文怎麼說

中文拼音 [zhǐlìngzhíhángsùlǜ]
指令執行速率 英文
instruction execution rate
  • 指 : 指構詞成分。
  • 執 : Ⅰ動詞1 （拿著） hold 2 （執掌） take charge of; control; manage; wield 3 （堅持） persist in; sti...
  • 行 : 行Ⅰ名詞1 （行列） line; row 2 （排行） seniority among brothers and sisters:你行幾? 我行三。where...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 率 : 率名詞（比值） rate; ratio; proportion
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 速率 : speed; rate; tempo
  1. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  3. It can also be applied to multithread scheme by adding thread identifier. our experiment results indicate that about 25. 8 % of all memory reference instructions in spec cpu2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. on average 9. 4 % data cache miss is reduced

    Speccpu2000程序運行結果表明，採用快速地址計算的自適應棧高速緩存方案， 25 . 8 %的訪存指令可以并行執行，數據高速緩存失效率平均降低9 . 4 % ， ipc值平均提高6 . 9 % 。
  4. Although gpu has a very high computing speed, algorithms implemented in cpu cannot be put to execute in gpu directly because of the discrepancy in instruction execution manner of the two. gpu ' s architecture is a high parallel simd instruction set system. to reimplement algorithms insufficient to run on cpu with programmable graphics hardware, it has to reconsider the data structures and procedures to implement them to make full use of the

    雖然gpu具有非常高的計算速度，但並不能將以前在cpu中實現的演算法直接放到gpu中來執行，這是因為gpu的指令執行方式和cpu不一樣， gpu的體系結構是一種高度并行的單指令多數據（ simd ）指令執行體系，所以要在可編程圖形硬體上實現在cpu中效率不高的演算法，就需要重新制定演算法實現的數據結構和步驟，以充分利用gpu并行處理體系結構帶來的性能優勢。
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