晶元測試 的英文怎麼說

中文拼音 [jīngyuáncèshì]
晶元測試 英文
chip testing
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 測 : 動詞1. （測量） survey; fathom; measure 2. （測度; 推測） conjecture; infer
  • 試 : 名詞（古代占卜用的器具） astrolabe
  • 測試 : test; testing; checkout; measurement
  1. The company possesses 6 sets of diode cmos chip equipment, producing three - inch 1. 2 million cmos chips per year. there is 3 productive flowing lines in the middle procession and 2 billion diodes were produced yearly. have yiguan machines and discrete machine for test, mimeograph and packing

    公司擁有前道生產二極體晶元設備6套，年產3英寸晶元120萬片中道具有3條生產流水線，年產二極體20億只后道具有測試列印包裝一貫機分立機。
  2. The function of ppi ( programmable parallel interface chip ) 8255 is realized through emulating the key waves and testing a chip

    通過波形模擬、下載晶元的測試，完成了計算機可編程并行接晶元8255的功能。
  3. Measurement challenges for on - wafer rf - soc test

    晶圓上測試射頻系統級晶元的挑戰
  4. It makes use of resource of the chip, realizes the development of every module, achieves distilling of telegraphese, builds up new frame, calculates the position and provides external interface. in the section of calculating the position, the author combines the two measures of carrier phase position and code position. finally, in the platform of matlab, the author completes the function simulation of main modules

    概述了接收機的設計原理;詳細描述了基於ti公司的tms320c6713dsp晶元的系統程序設計中各模塊的實現，利用該晶元的資源，實現各模塊的調度，完成對導航電文的提取，重新組幀，定位解算以及對外介面;在解算部分，把載波相位定位與碼測距定位相結合，利用載波相位對偽距的平滑來提高定位精度;在matlab平臺下進行了各模塊的功能模擬測試，以模擬結果的圖表來分析說明了載波相位平滑偽距的兩種演算法能使定位精度有一定的提高。
  5. It shows that the injection quantity and the difference of temperature distribute as a parabola which is at the same load, and the minimum of the parabola corresponds to the optimum quantity of injection ( g ). under the condition that the quantity of injected mass, the air speed and the heat quantity is respectively g, v and q, the research demonstrates that the pentium iv chip ' s temperature variation can be controlled under 40c and work normally when the wind speed overpass 1. 5m / s and the power dissipation of the chip is 60w. otherwise this paper calculates the flooding limit of thermosiphon with several different methods

    對其充灌量、散熱量、電子元件（ cpu模擬晶元）表面與環境溫度之差及通風、流速的影響進行了系統的測試，發現充液量與溫差的關系在負荷不變時呈拋物線分佈，其極小值點對應的充液量是最佳充液量g 。在充液量為g時，對風速v 、散熱量q進行的研究表明，當風速超過1 . 5m / s后，奔騰晶元在60w發熱條件下晶元溫度小於40 ，能滿足長期正常工作。
  6. Chapter 4 studies scheduling algorithm of the core node to implement on single adsp2191. the result shows that a single adsp2191 chip can ’ t satisfy the bhp processing delay request and parallel processing is inevitable. chapter 5 primarily studies the core node ’ s scheduling algorithm with many dsp parallel process. details of lauc - vf scheduling algorithm analysis data flow organization and mission distribution are argued. the results of software simulation and hardware debugging indicate that many dsp parallel processing is effective and coincident with the system ’ s demand

    結果表明單片adsp2191晶元不能夠滿足核心節點對bhp的實時處理要求，必須多dsp并行處理。第五章研究了核心節點調度演算法的多dsp并行處理。對多bhp批調度演算法的實現進行分析，探討了多bhp處理任務的的劃分和分配方案;多dsp間數據通信和傳輸的dma實現;最後對多處理器并行的處理時間進行模擬測試分析。
  7. Part two : design the schematic of the intelligent communication card ; to apply protel99 software to design sch and pcb charts, then send them to the factory ; to debug on the hardware and test on can bus chip ; to program assemble language control and can bus communication software of the intelligent communication card and debug on the super ice16 simulator ; to utilize the super ice 16 simulator to debug the control programs of the communication card online ; link to control card and debug the can bus communication program online ; to debug the system on eprom

    第二部分：設計can總線智能通信卡的硬體電路，應用protel99設計軟體繪制原理圖及印刷電路板圖，並送廠製作板卡電路板:智能通信卡硬體製作和can總線晶元調試;編寫通信卡控制及can總線通信匯編語言程序並編譯;在superice16模擬器上在線模擬調試控製程序;連接系統控制卡，模擬調試can總線通信程序;程序燒入eprom晶元，進行系統eprom模擬調試;介面系統驅動程序及測試軟體調試。
  8. In this thesis, scanning force microscopy ( sfm ) was used to study the nanoscale electric phenomena of the surface and interface properties of ferroelectric thin films. the experimental setup was calibrated by measuring potential distribution of the working resistance of integrated chip

    在實驗儀器的驗證方面，選用集成電路晶元測試單元中的埋置條形電阻作為檢測對象，在電阻兩端外加直流偏壓后檢測電阻的電勢分佈，在已知電阻上電勢分佈的前提下，驗證了開爾文力顯微鏡檢測微區表面電勢的可靠性。
  9. To debug on the hardware, eliminate circuitry errors, and test on every chip. 3

    對板卡硬體調試，線路排錯，晶元測試； 3
  10. If we can eliminate the bad chips in advance of the testing stage, then the non - meaningful waste can also be decreased in the later process

    若能及早將不良的晶元在晶圓測試階段即予以剔除，便能減少後段加工工序中不必要的浪費。
  11. Based on that, the author simulated most of the sub - block circuits and whole chip circuit by applying eda tools hspice. the simulation results indicate that the ic has achieved the expectation,

    理論分析、模擬結果和晶元測試數據表明，在典型情況下，該電路的電流控制精度相對誤差和匹配相對誤差可以控制在0 . 5 %以內，達到了預定設計目標。
  12. Bluetooth headset main chip testing f

    藍牙耳機主晶元測試架
  13. Test results show that this adc achieves the snr of 90 db and distortion ratio of 0. 0248 % for a 20khz signal bandwidth while operating under a single 3. 3v supply

    晶元測試結果顯示其信噪比達到90db ，總諧波失真0 . 0248 % ，基本達到了預期的設計指標。
  14. We aslo get the theory of verification test and design debug discussed, and then, some work on the verification test of this integrated circuits have been done. for the sake of finding out the reason of noise occurring in circuit of oscillator, we probe into causation of technics and mechanism

    論文最後基於晶元測試理論，針對晶元流片后的部分測試結果，對振蕩出現的噪聲問題給出了初步分析，並結合投片工藝探討了工藝原因與產生機理。
  15. Test results show an excellent performance of the chip

    晶元測試結果顯示晶元性能優異，達到預期的設計要求。
  16. Study on test control for system - on - a - chip based on test data slicing

    基於數據切片的系統晶元測試控制技術研究
  17. Because the truly characteristic of random numbers ca n ' t be proved by testing the chip, it ' s very important to guarantee it in the theory

    由於隨機數的真隨機性不可能在晶元測試時得到證明，因此在理論上保證它的真隨機性顯得尤為的重要。
  18. The testing of the chip is faced with very serious challenge, the cost of testing is always rising, and even larger than the designing and manufacturing cost

    晶元測試遇到了前所未有的挑戰，測試費用越來越高，出現了設計、生產費用與測試費用倒掛的局面。
  19. With the sharp development of lsi and vlsi, the integration of chip gets denser and denser. but the extra ports for testing is limited and test is more difficult than before. we even must spend more time and money on chip testing rather than chip design

    大規模集成和超大規模集成電路迅速發展，使晶元的集成度越來越高，而供外部測試的引腳卻很少，測試問題日趨困難，甚至使晶元測試比晶元本身的設計和生產要付出更高的代價。
  20. The thesis is composed of 9 parts : the background, significance, main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2, the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7, a fixed equalizer for 2. 5gbps transceiver is described ; in chapter 8, layout design and measured results are discussed ; at last, the conclusions are drawn in chapter 9. during period of finishing the thesis, i read lots of literatures about the interface circuits in high - speed data transmission system, studied their principles and design techniques, and designed : 1 、 the line driver for 2. 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2. 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1. 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver

    論文由9部分組成：在第一章引言中介紹了論文的背景、意義、國內外研究現狀，以及論文的主要內容和創新；第二章以千兆位以太網為例，從系統的角度介紹了高速數據傳輸系統介面電路的主要功能和性能指標；第三章分析了高速數據傳輸系統的傳輸介質的頻率特性和模型；第四章描述了線驅動器的設計原理及其電路實現；第五章描述了高速數據傳輸系統的均衡原理；第六章描述了適用於1 . 25gbps基帶銅纜收發器系統的自適應均衡器的設計原理和電路實現；第七章描述了適用於2 . 5gbps基帶銅纜收發器系統和1 . 5gbps串列硬盤介面（ sata ）收發器系統的固定均衡器的設計原理及其電路實現；在第八章中分析了電路的版圖設計及晶元測試結果；最後，第九章總結了全文。在完成論文期間，查閱了大量的有關高速數據傳輸系統介面電路方面的文獻，較系統地學習了線驅動器、傳輸線和均衡器等方面的理論知識和電路設計原理，設計了用於： （ 1 ） 2 . 5gbps基帶銅纜收發器系統的線驅動器； （ 2 ） 2 . 5gbps基帶銅纜收發器系統的固定均衡器； （ 3 ） 1 . 5gbpssata系統的固定均衡器； （ 4 ） 1 . 25gbps基帶銅纜收發器系統的自適應均衡器。
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