譯碼門 的英文怎麼說

中文拼音 [yìmǎmén]
譯碼門 英文
decoding gate
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  1. Owing to the recurrent stoppages of work through the air raids, arrears had accumulated in the cipher branch.

    由於在空襲中工作屢屢停頓，密碼部門積壓了許多未譯的電報。
  2. The designing process of the edac circuit is described in the paper. the time simulation is analysed, too. the designment of the circuit has access the hardware debug, and can woks normally

    此外還將第一輪設計中的基本邏輯器件如與、或、非門以及諸如244 、 255 、譯碼器等小規模元器件都集成到fpga內部來實現。
  3. In data security, the science and study of methods of breaking ciphers

    在數據安全領域中，對破譯密碼的方法進行研究的一門學科。
  4. Low power design methods of setting threshold on viterbi decoder

    譯碼器設置門限的低功耗設計方法
  5. In order to prevent encrypting system from being broken, the variant non - super increasing sequence is used as the trapdoor knapsack vector to improve the security of public key cryptosystems

    為防止破譯，本文採取變形的非超遞增序列作為陷門背包向量，來提高背包公鑰密碼體制的安全性。
  6. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  7. This system presents us various kinds of user interfaces ( such as thin - client ui ), further more, to facilitate further research and provide a scientific foundation to ensure flight safety and daily monitor, other extended interfaces ( including network interface, data analysis interface, decode interface and etc ), are also provided by the system

    該系統由數據採集、譯碼、實時數據處理、實時監控模擬再現等模塊組成，系統還提供用戶介面、網路介面，數據分析介面，譯碼擴展介面等。該系統可以應用於航空公司機務維修等部門，結合地空數據鏈系統，為保障飛機飛行安全以及日常監控提供科學的依據，同時也為飛機油耗優化、技術評估等提供數據支持。
  8. The viterbi decoder with hard decision designed by the paper, is aimed at ( 3, 1, 9 ) convolutional coding. the data rate is 9. 6kbps. the data rate received by the rake receiver is spreaded by 127 - bit spread sequences, added pilot signals and modulated by qpsk

    該課題所設計viterbi譯碼是針對（ 3 ， 1 ， 9 ）卷積碼的硬判決譯碼，數據速率為9 . 6kbps ; rake接收機所接收的數據是擴頻因子為127 、加入導頻且經qpsk調制的擴頻信號，使用verilg硬體描述語言在xilinx公司的ise環境下在用現場可編程門陣列（ fpga ）來實現viterbi譯碼器和rake接=收機的功能。
  9. Pls remit usd _ _ by t / t to jp morgan chase bank n. a, new york. ( chasus33 ) for credit of agricultural bank of china, xiamen branch ( aboccnbj400 ) in foaour of _ _ ( the beneficiary " s name ， a / c no. ， address and tel. no

    譯:請將美元_ _電匯至美國摩根大通銀行紐約分行，轉入中國農業銀行廈門市分行帳戶，註明收款人名稱、帳號、地址、電話號碼
  10. The c compiler would automatically insert the back door into the login program, so there was no need to keep the back door in the source of the login command

    C編譯器將自動把后門插入到login程序中，所以，不需要在login命令的源代碼中保留後門。
  11. To persistence the objects there are two common approach. one approach is that structured query language ( sql ) codeis embedded in the source code of your classes. the other approach is that sql statements for your business classes are encapsulated in one or more " data classes. " the disadvantage is that it directly couples your business classes with the schema of your relational database, implying that a simple change such as renaming a column or porting to another database results in a rework of your source code

    實現在關系數據庫存取對象，常用的做法有：一種方法是在對象中直接編寫sql代碼來存取對象，另一種方法是將sql代碼在專門的數據類（或存儲過程）中編寫，但著兩種方式都使得對象模型與關系數據庫模式的耦合度大，不容易維護，因為關系數據庫模式的微小改動，都將導致應用程序的重新編譯。
  12. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
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