譯碼邏輯 的英文怎麼說
中文拼音 [yìmǎluó]
譯碼邏輯
英文
decode logic-
In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework
另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。The designing process of the edac circuit is described in the paper. the time simulation is analysed, too. the designment of the circuit has access the hardware debug, and can woks normally
此外還將第一輪設計中的基本邏輯器件如與、或、非門以及諸如244 、 255 、譯碼器等小規模元器件都集成到fpga內部來實現。3. coding design and software programming. 4
3 、可編程邏輯的譯碼設計以及匯編語言編程。Making logical designs with the integrated decoder
用集成譯碼器進行邏輯設計In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld
本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function
本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。An application of logic devices able to program to the decoding circuit
可編程邏輯器件在譯碼電路中的應用The integrated debugger lets you find and fix runtime and logic errors, control program execution, and step through code to watch variables and modify data values
閱讀編譯器信息，集成的調試器允許你找出並修復運行和邏輯錯誤，控製程序執行，並步進代碼以監視變量並修改數據值。Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details
Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit
本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。In the stage of generate the target code, we pass to compile the machine logic source program, to generate the target code in the form of machine code
在目標代碼生成階段，我們通過對機床邏輯源程序的編譯，生成機器碼形式的目標代碼，對分析過程中產生的錯誤進行分析處理。The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method
這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。We only need to compile the machine logic source program once, and hereafter we can run target code every time
我們只需要對機床邏輯源程序編譯一次，以後每次直接運行編譯所生成的目標代碼就可以了。Then, the author specially studies the characteristic of system architecture of the dsp, paints schematic principle diagram and pcb diagram of the hardware circuit system, writes the program decoding and partial data processing of the cpld, adopting verilog hdl hardware describing language
然後，研究了dsp晶元結構體系的特點，繪制了硬體電路系統的原理圖和pcb圖，且採用veriloghdl硬體描述語言編寫了復雜可編程邏輯器件（ cpld ）的譯碼與部分數據處理程序。分享友人