連接埠號碼 的英文怎麼說
中文拼音 [liánjiēbùháomǎ]
連接埠號碼
英文
port number- 連 : Ⅰ動詞1 (連接) link; join; connect 2 (連累) involve (in trouble); implicate 3 [方言] (縫) ...
- 接 : Ⅰ動詞1 (靠近;接觸) come into contact with; come close to 2 (連接; 使連接) connect; join; put ...
- 埠 : 名詞1. (碼頭) pier; port; wharf; jetty 2. (有碼頭的城鎮) port city3. (商埠) commercial port
- 號 : 號Ⅰ名1 (名稱) name 2 (別號; 字) assumed name; alternative name3 (商店) business house 4 (...
- 碼 : Ⅰ名詞(表示數目的符號或用具) a sign or object indicating number; code Ⅱ量詞1 (指一件事或一類的...
- 連接 : connect; fit together; link; marry; mate; joint; association trail; linkage; concatenate; concate...
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The whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of spwm and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the synthesizable and reusable code. the functional stimulation uses the nc - verilog of cadence
系統設計是基於spwm的實現演算法和設計指標要求,對系統劃分模塊和對各個模塊進行信號連接;模塊設計是設計每個模塊內部電路結構,並用verilog語言編寫可綜合可復用代碼;功能模擬使用的工具是cadence的nc _ verilog ,首先對每個模塊進行功能模擬,模擬通過之後,把所有模塊代碼組合在一起,構成整個系統代碼,在外部輸入埠加激勵,對整個系統進行功能模擬。The main process includes following : system design, module design, function simulation, time simulation and hardware verification. the whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of uart and the requirement of design. the module design is to design inner circuit structure of each module and uses verilog language to code the code
系統設計是基於uart的實現演算法和設計指標要求,對系統劃分模塊以及各個模塊的信號連接;模塊設計是設計出每個模塊的功能,並用verilog一hdl語言編寫代碼來實現模塊功能;功能模擬和時序模擬使用的工具是以dence的nc _ veri109 ,首先對系統的每個模塊進行功能和時序模擬,模擬通過之後,將整個系統的代碼在外部的輸入埠加上激勵,對整個系統進行功能和時序模擬;硬體驗證是用fpga對系統進行了功能驗證。
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