邏輯驗證系統 的英文怎麼說

中文拼音 [luóyànzhèngxìtǒng]
邏輯驗證系統 英文
logic verification system
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 驗 : 動詞1. （察看; 查考） examine; check; test 2. （產生預期的效果） prove effective; produce the expected result
  • 證 : Ⅰ動詞（證明） prove; verify; demonstrate Ⅱ名詞1 （證據） evidence; proof; testimony; witness 2 （...
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 統 : Ⅰ名詞1 （事物間連續的關系） interconnected system 2 （衣服等的筒狀部分） any tube shaped part of ...
  • 邏輯 : logic
  • 驗證 : test and verify; checking; proving; testing; confirmation; [數學] corroboration; inspection; veri...
  • 系統 : 1. （按一定關系組成的同類事物） system 2. （有條理的;有系統的） systematic
  1. For seminal work introducing temporal logic into computing science and for outstanding contributions to program and systems verification

    他將時序邏輯引入計算機科學，為程序和系統的檢測驗證方面提供一種有力的工具。
  2. After discuss the structure and character of operating system qnx and inter - process communication between pc ' s running qnx or windows, the paper describes the structure, function and flow chart of mission planning software which is developed in qnx, and narrates the course of simulation co - debug experiment, dynamically showing the results of the mission planning in the case of " ocean physiognomy reconnaissance ", and proving the logical correctness and feasibility of task serial produced by mission planning

    在論述了多任務、實時操作系統qnx的結構特點以及基於qnx與windows運行的pc機之間網路進程通信的基礎上，本文描述了在qnx上開發的使命規劃軟體的結構功能和流程圖，並敘述了模擬聯調實驗的過程，動態地顯示了「海洋地貌勘測」這一案例使命規劃的結果，並證明了使命規劃所得的任務序列在實際運行中邏輯的正確性與可行性。
  3. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  4. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  5. In the design, we make use of two eda tools max + plus ii and protel99. because of the using of complex programmable logical device ( cpld ), we can keep untuched the original hard circuit in design and realization of counting card, so it inherited the advantage of its predecessor. in order to quantitatively analyze the performance of data acquisition system with fifo cache, we introduced the queueing theory to build mathematic model to test its quality

    在設計中藉助了max + plusii和protel99兩個eda設計軟體。由於採用了復雜可編程邏輯器件cpld ，使得在計數卡的設計和實現中不用更改原硬體電路，對原設計的優點有很好的繼承。在驗證系統改進性能時，引入排隊論建立了數學模型對系統的工作性能進行定量分析，證明其達到了設計要求。
  6. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    搭建了一個驗證系統，通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  7. Thus, the complexity of the logical framework is hidden but the benefits of using type theory and its related tools are retained, such as precision and machine - checkable proofs

    由此，邏輯框架的復雜性就被隱藏起來了，同時我們還保留了精確性和機器驗證等使用類型理論系統及其相關工具的優點。
  8. The authors have formalized a specification language and logic - calculus in lf, together with useful lemmas, and a user - oriented syntax has been designed

    在本文中，我們考慮并行系統的驗證領域，並在lf中將特定論域的規范描述語言ccs和相關邏輯m - culculus形式化。
  9. A widely distributed software package that supports the formal verification of distributed systems - is an example of temporal logic model checking for hardware verification

    一種支持分散式系統的正式驗證且廣泛發布的軟體包是用於硬體驗證的時態邏輯模型檢查的示例。
  10. Firstly, for the purpose of research and verification of multithread microprocessor, a superscalar microprocessor model armp - v2 is built on the basis of armp microprocessor ; secondly, the issue logic is not only the critical path in a superscalar microprocessor, but also critical to the performance of a multithreaded microprocessor with superscalar execution core

    首先，在設計的嵌入式微處理armp的基礎上進行改進，提出了一個超標量處理器模型，用於多線程處理器系統結構的研究與驗證。其次，指令發射邏輯是超標量處理器中的關鍵路徑，也是制約執行單元為超標量結構的多線程處理器主頻提高的關鍵因素。
  11. A algorithm is presented to identify dynamic crosstalk noise. in the course of dynamic crosstalk noise identification, hybrid timing analysis is used to provide accurate signal arrival time, which can provide more accurate timing information than static timing analysis. at the same time, a novel test generation is chosen to verify the correlation of signals. so dynamic crosstalk noise can be identified by these accurate timing and logic information

    提出了動態串擾噪聲的識別演算法.針對基於傳統靜態時序分析的結果過于保守的缺點，本演算法引入了混合時序分析，縮小了時間窗區間，為動態串擾噪聲的識別提供了準確的時序信息，與此同時，通過測試生成來驗證信號間的邏輯關系，根據這些準確的時序及邏輯信息，識別出動態串擾噪聲
  12. Then, with considering the technical problem that existed in the applying process of the frequency modulation inductance sensor, the integration of the data acquisition circuitry and interface circuitry of this kind of sensor have been studied and the circuitry system with better performance using pld has been developed. at the end of this thesis, the measuring software and some experiments that tests the whole system are introduced

    然後，針對調頻式電感傳感器在過去使用中遇到的技術難題，對該類傳感器數據採集及微機介面電路進行了集成化研究，採用可編程邏輯器件技術設計出了高性能的儀器數據採集及控制系統的硬體電路系統，最後編制了測量軟體且進行了一系列驗證系統性能的測量實驗。
  13. In order to make the speed of the function simulation faster, the system adopting vhdl ( very high - speed integrated circuit hardware description language ) to make simulation faster, at the same time this make it easy to transplant the circuit to other kinds of isp chips

    為了提高模擬的速度，對部分電路採用vhdl語言進行邏輯描述。通過實驗證明，在微波測距儀中採用在系統可編程邏輯器件，收到了很好的效果。
  14. Using bzl logic, security, anonymity and tracing ability of the digital - cash is verified. the protocol proves strong by using the factual system and being verified by the bzl logic

    通過在電子交易系統的實際應用和bzl邏輯的形式化驗證，證明了提出的數字現金協議是一個強壯的協議。
  15. Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products

    討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。
  16. The three main methods ( neural network, fuzzy logic system and ga ) of intelligent control are studied in the paper, and they are proved to be reasonable and practical

    本文對智能控制中的三個主要方法神經網路、模糊邏輯和遺傳演算法在船舶動力定位系統中的應用進行了全面的分析和研究，並通過模擬實驗驗證了所研究技術的合理性和實用性。
  17. Combinations of igbts controlled by four - step current commutation algorithm, was implemented by the cpld, which was also forecasted and validated by the simulation and experiment

    為進行對矩陣式變換器系統的實驗研究，採用cpld （復雜可編程邏輯器件）實現了igbt組合雙向開關的四步換流邏輯控制，並通過模擬和實驗進行了預測和驗證。
  18. Secondly, the thesis analyzes the logic of the source codes of timedb to research the constructive methods and principles of temporal database management system. it shows how timedb can translate the tddl, tdml and tdql into standard sql statements. finally, a prototype, vehicle team system, is successfully developed using the timedb ' s apis

    首先分析timedb支持的時態查詢語言atsql2的擴展方法和原理，同時結合實例說明atsql2的使用方法；接著深入分析timedb的源代碼邏輯結構，深層次地分析tddl 、 tdml 、 tdql的轉換方法和原理；最後應用timedb的api ，成功開發了「車隊管理系統」 ，驗證timedb的先進性及其在時態數據管理上的不足。
  19. This section provides information on how to create a deployment diagram, bind applications within the system to logical servers, and validate system deployment

    本節介紹了如何創建部署關系圖，以及如何將系統內的應用程序綁定到邏輯服務器和驗證系統部署。
  20. The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
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