門陣列法 的英文怎麼說

中文拼音 [ménzhènlièfǎ]
門陣列法 英文
gate array a roach
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  • 陣 : Ⅰ名詞1 （作戰隊伍的行列或組合方式） battle array [formation]: 布陣 deploy the troops in battle fo...
  • 列 : Ⅰ動1 （排列） arrange; form a line; line up 2 （安排到某類事物之中） list; enter in a list Ⅱ名詞1...
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 陣列 : [統計學] array陣列處理機 array processor; 陣列印表機 array printer; 陣列雷達 [電學] array radar
  1. At secondly, for depressing the noise in ir images, we make a deep research in median filter and it ' s algorithm architecture, then we present a improved method based on the control bit look ahead structure and implement it in fpga. at last, we resolved the data communication problem in the multiprocessor ir image processing system and and complete the system debug

    然後，針對校正後圖像中噪聲干擾的問題，深入研究了中值濾波的特性和演算法結構，提出了具有超前控制位的max - min中值濾波器的改進結構，在現場可編程門陣列fpga上設計實現了該中值濾波器，並進行了驗證。
  2. The method of design of system on chip ( soc ) based on the field program gate array ( fpga ) is also introduced

    並對課題中採用的基於現場可編程門陣列（ fpga ）的片上系統（ soc ）設計方法進行了介紹。
  3. In this study, the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design, we have obtained samples of integrated circuits test structures manufactured by wuxi csmc - hj using their 0. 6 - m cmos process

    在研究中，我們將降低輻射效應的設計方法應用到門陣列設計中，獲得了華晶上華半導體有限公司採用0 . 6 m的cmos工藝生產的集成電路樣片，具有100krad （ si ）的抗總劑量輻射能力。
  4. In the software design part, the image encoding is realized with huffman encoding on the bubbling up sorting method for 256 gray - color values. the result of the encoding and encoding efficiency are displayed in the list box. in the hardware design part, on the basis of the characteristic and development of the embedded system hardware, the code joint is realized with the fpga and vhdl

    在紅外虛擬鍵盤的軟體實現部分，採用哈夫曼（ huffman ）編碼的方法實現了圖像編碼，利用冒泡法對256個灰度值進行排序，最後將編碼結果以及編碼效率等以列表框的形式顯示；在硬體設計部分，基於目前嵌入式系統硬體的特點及發展，採用可在線修改的現場可編程門陣列fpga （ fieldprogrammablegatesarray ）技術以及高速集成電路硬體描述語言vhdl （ veryhighspeedintegratedcircuitshardwaredescriptionlanguage ）等方法實現圖像處理中的碼字拼接功能。
  5. Digital beam forming ( dbf ) is a kind of new technique which based on the antenna beam forming and the well - developed digit signal processing. the technique should convenient obtains high resolution and low sub beam by sufficiently utilizing of the space message received by array antenna. and make the technology of beam scanning, self - calibrating and adaptive beam should be realized easily

    數字波束形成（ dbf ）是在天線波束形成的基礎上，引入先進的數字信號處理方法后建立起來的一門新技術，這種技術可以充分利用陣列天線檢測到的空間信息，並易於獲得超解析度和低副瓣，實現波束掃描，自校準和自適應波束形成等。
  6. In order to resolve the contradiction between real - time and arithmetic complex in the television tracking capture system, the paper designs the real - time target track processing system which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    摘要為解決電視捕獲跟蹤瞄準系統中系統的實時性與演算法復雜性之間的矛盾，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  7. The system used hight - performance dsp ( tms320c6202 ) to realize the real - time image object tracking algorithm, used large - scaled programmable logical array cpld to control logic and field programmable gate array fpga to preprocessing the image

    其中運用了高性能dsp （ tms320c6202 ）完成實時圖像目標處理演算法，並結合大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理，滿足了系統的實時性。
  8. At first, we introduce the working flow of ir image processing and the structure of the image processor, then we present the goal of the design : image pre - processing and data communication. in the part of the image pre - processing, the factors causing the nonuniformity of fpas are analyzed particularly, and several. resolutions are presented, which characters are illustrated at last. according to the design requirement, we decided to implement the two - point nonuniformity correction method in fpga

    在圖像預處理部分，首先就紅外成像傳感器非均勻性的成因進行了詳細分析，總結了紅外成像傳感器非均勻性校正的主要方法，分析了各種方法的優缺點；根據成像制導信息處理機實時處理的要求，利用現場可編程門陣列實現了基於浮點運算的兩點法非均勻性校正模塊。
  9. The real - time target track processing system is designed which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    為了解決演算法復雜性及滿足工程實時性，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  10. It begins form the discussion the knowledge of the gaussian filter and the laplacian operator, which are the base of the marr method. and it is followed by the detail discussion of such as : the 2g （ laplacian of gaussian ) filter, the template log ( laplacian of gaussian ), the meaning of laplacian of gaussian in human vision, edge detection and neurophysiology. with different template to different size of target, the small target can be separated from the background by this small infrared target detection method

    從marr演算法的理論基礎? ?高斯平滑濾波器與拉普拉斯運算元的相關知識以及Ｍ ａ ｒ ｒ的計算視覺理論基礎開始，進行了2g （ laplacianofgaussian ，高斯?拉普拉斯）濾波器、 log （ laplacianofgaussian ，高斯?拉普拉斯）模板以及2g濾波器在人類視覺、邊緣檢測、邊緣處理的物理意義以及神經生理學意義方面的分析討論，提出了易於fpga （ fieldprogrammablegatearray ，現場可編程門陣列）實現的基於marr計算視覺的紅外圖像小目標檢測方法。
  11. From october 24 to november 1, 2003, formosan members of the supreme master ching hai international association inspired residents of the offshore island of kinmen with a series of truth - sharing and public - interest activities entitled heavenly grace manifests in human love. before undertaking the project, the initiates held a retreat at the jinsha center in kinmen on october 22 - 23 to pray for world peace and ask for gods blessings to ensure their success

    清海無上師世界會福爾摩沙同修於10月24日至11月1日在金門地區舉辦天地有情人間有愛一系列弘法暨公益活動，為金門民眾帶來一陣愛的旋風。同修並於10月22 23日兩天在金門金沙道場舉行一場禪二，祈求上帝加持，讓此次活動能夠順利圓滿，同時也為世界和平祈福！
  12. This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions

    本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。
  13. Abstract : a design method of using gal to make a constant current source is introduced ， proving a new method of current stabilization by means of driving regulated transformer by a controlling device. experimental results are given to demonstrate effectiveness of the method

    文摘:主要介紹以可編程門陣列器件構成恆流源核心控制電路的設計思路，通過機電自控裝置驅動可調變壓器實現新的穩流方法，實驗證明這一方法是可行的。
  14. This paper has designed and finished motor controller with field programmed gate array ( fpga ) chips made in altera and analyzed the ways to realize the speed adjusting of bldcm ( brushless direct current motor ) with this controller

    本論文利用altera公司的現場可編程門陣列（ fpga ）晶元完成了電機控制器的設計、製造和調試並在此基礎上分析研究了利用此控制器對無刷直流電機進行調速控制的方法。
  15. We focus on the carrier synchronization method, the circuit and its parameters design, the performance simulation and the circuit implementation in field programmable gate array ( fpga )

    重點研究載波同步方法，設計電路及參數，模擬同步性能，並在現場可編程門陣列（ fpga ）上實現同步電路。
  16. Due to intellectual asset in the form of copyright and / or patent, there are no available rs coding and decoding modules for calling for in scientific research exploitation. furthermore, the configuration and algorithm are rather complicated. it is demanding to fulfill this part of module unit based on fpga and to form the kernel for calling for

    由於知識產權的關系，在科研開發中沒有現成的rs編解碼模塊可供調用，而有關結構和演算法又較為復雜，因此迫切需要在fpga （現場可編程門陣列）上完整實現這部分模塊單元，並形成可供調用的內核。
  17. This fact implies that the fractal algorithm is very effective and in practical. 2 ) by combining the tabu search and the clustering technique, we propose a hybird algorithm to solve the placement problems, both for the bbl and the gate - array placement. simulation results show that our hybird algorithm is of robustness and effectiveness, it is expected the algorithm is also uesful in other optimization problems. to testify the feasibility of using various computational intelligent algorithm, such as neural networks, genetic algorithm and ant colony system approach in solving a

    2 ）首次將禁忌搜索演算法與結群技術相結合，並將其分別應用於門陣列布局和bbl布局中，計算機模擬結果表明該演算法魯棒性強、有效，適應性廣，適用於大規模門陣列布局和bbl布局問題， 3 ）分別用神經網路技術、遺傳演算法和蟻群演算法對兩端線網布線問題進行了研究，並對結果進行了分析比較。
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