instruction processor 中文意思是什麼

instruction processor 解釋
指令處理機
  • instruction : n. 1. 教育，教導。2. 教訓，教誨。3. 〈 pl. 〉 指令，訓令，指示，細目。
  • processor : n. 1. 〈美國〉農產品加工者；進行初步分類的人。2. （數據等的）分理者；【自動化】信息處理機。
  1. The designed model is compiled into custom instruction of nios processor via sopc interface, and made up hardware accelerator interface model

    最後將該模塊通過sopc介面編輯成nios處理器的用戶指令，組成硬體加速器介面模塊。
  2. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  3. In this paper, an embedded 16 - bit processor core is designed, based on the characteristics of the wireless communication algorithm and instruction level acceleration technology

    文章結合無線通信處理演算法的特點，利用指令級加速技術，設計了一種基於無線通信中復數運算的16位嵌入式處理器核。
  4. Instruction means that the processor walks through the secondary source and applies templates as it goes along

    指令意味著處理器遍歷輔助源文檔，並在遍歷過程中應用這些模板。
  5. This paper introduces a ip phone system based on dsp and arm reduced instruction set computer ( risc ) double core processor

    本文介紹的是一種基於dsp和arm精簡指令集處理器（ risc ）雙cpu處理器方案研發的ip電話系統。
  6. The verification process for a digital signal processor with very long instruction word ( vliw ) named thuasdsp2004, which is developed by tsinghua university microelectronic institute sponsored by national natural science foundation, is analyzed at the register - transfer level in this paper

    本文介紹在國家自然科學基金的資助下，由清華大學微電子研究所設計的具有超長指令字（ verylonginstructionword ， vliw ）體系結構特點的數字信號處理器thuasdsp2004的rtl級功能驗證工作。
  7. In a computer, a functional unit that interprets and executes instructions. note : a processor consists of at least an instruction control unit and an arithmetic and logic unit

    計算機中，解釋並執行指令的一種功能單元。注：處理器至少包含有一個指令控制器和一個算術與邏輯運算器。
  8. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  9. 3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies. to improve cache performance under sma model, the paper introduces hardware software co - operative optimization

    3針對多線程模式下訪存負荷加重的問題，為sma模型設計了軟硬體協同預取機制，並為sma模型設計了cachefilter來消減無效預取。
  10. It has a balance design, which regards the reduced instruction frame as principle but do not abandon complex instructions. so, arm processor can obtain high - performance, at the same time it is low - power processor

    它以精簡指令構架為主又不放棄與復雜指令平衡的設計，使得arm處理器在獲得高性能的同時又能做到低功耗。
  11. The micro - kernel architecture is suitable for dual - core environment, because the micro - kernel architecture has a good module and its size is small. based on the analysis the source code and the dual - core hardware architecture, modify the module in order to suit for the dual instruction stream environment of the dual - core processor

    在對代碼分析的基礎上，總結出代碼中所體現出現的內核各模塊的內部結構，再結合雙核處理器的硬體特點，對模塊進行修改，相當于對模塊作加法運算，使其滿足雙核處理器的雙指令流體系結構。
  12. The digital signal processor becomes the preferred utility for realizing digital arithmetic rapidly and precisely relying on its particular hardware and instruction architecture

    而dsp （數字信號處理器）以其特有的硬體體系結構和指令體系成為快速精確實現數字信號處理演算法的首選工具。
  13. It has been an exigent task to reduce the difficulty of functional verification, cutting down the ratio of verification in the whole design duration, while assuring the coverage of functional verification when designing a high performance processor to solve this problem, the concept of random instruction testing has been introduced here. thus not only a lot of verification engineers " burdens of hand writing test is reduced, but also the influence of man - made factor in the process of testing

    如何在保證效果的同時，降低驗證工作的難度，減少驗證在整個設計周期的比率，已經成為高性能嵌入式處理器設計所迫切需要解決的一個問題。為了解決這個問題，引入了隨機指令測試的概念。這樣一來就可以大大減輕驗證工程師在晶元驗證時人為書寫大量測試的負擔，同時又可以減輕了人為因素在驗證過程中的影響，達到更好的測試效果。
  14. Traditional reduced instruction set computer ( risc ) and digital signal processor ( dsp ) have different application areas due to their different instruction set architecture ( isa ) and micro - architecture

    傳統的精簡指令集處理器（ risc ）和數字信號處理器（ dsp ）各自具有不同的指令集結構和微結構特點，適合於不同的應用領域。
  15. 3 ) the instruction - level parallel calculation of streamlines on 3d curvilinear grids has been implemented firstly by using the streaming simd extensions ( sse ), which are a set of extensions of the intel pentium hi / 4 processor. compared with the conventional algorithm, sse - based algorithm coded by vector class library enhances performance about 55 %, and coded by inlined - assembly is about 75 %

    ） pentium （ pentium4 ）處理器的流simd擴展（ sse ） ，首次實現了3d曲線網格流線計算的指令級并行，與傳統演算法相比，向量類庫編碼實現的sse演算法將性能提高了55左右，嵌入匯編實現提高了75左右。
  16. And asip ( application - specific instruction set processor ) based on risc core is the key to integrate other system

    而基於risc核的專用指令處理器（ application - specificinstructionsetprocessor ）是構成其它更大系統的關鍵。
  17. To solve the problem of exponential space in the instruction - set automated design for the application specific instruction set processor ( asip ), a formular clustering integer linear programming model ( cim ) is proposed, which can decrease the exploration space effectively utilizing function dependencies between instructions

    摘要提出集束式整數線性規劃形式化模型，利用指令間的功能依賴性解決專用指令集處理器中指令集自動定製的指數性空間問題。
  18. In the checking process of embedded processor, random instruction testing plays an important role to reduce the design period of processor

    在嵌入式處理器的驗證過程中，隨機指令測試起到了非常重要的作用，利用它，可以縮短處理器設計周期。
  19. The simulation of the addressing mode provides the possibility for the instruction simulation, and the simulation of the interrupt, timer and serial port lets the simulator implement the functions of the interrupt, timer and serial like a processor, and the program control simulation provides the possibility for running the program. this function is also the base for debugging program, which can set step running mode, set break points by using this program

    尋址方式的模擬為指令的模擬提供了可能，中斷、定時器和串列口的模擬使模擬器可以象處理器一樣完成中斷功能、定時功能和串列通訊功能，程序控制的模擬為程序運行提供了可能，這一功能又是調試程序的基礎，通過這個程序程序可以單步執行，設斷點執行。
  20. To enhance the quantum co - process unit ' s executing efficiency, we have proposed the dynamic schedule technique of quantum instruction, which references the idea in classic processor

    該方案中使用了量子指令動態調度技術，有效提高了量子計算處理器的執行效率。
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