memory bus 中文意思是什麼
memory bus
解釋
存儲棲線-
A " real " address, the value that must be placed on the system address bus to select a physical memory bank or device
物理地址：真實的地址，其值必須被置於系統地址總線中用於選擇物理存儲位置或者設備。 -
The microprocessor uses the address bus to locate data stored in memory.
微處理機使用地址總線設定在存貯器中存貯的數據的地址。 -
Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel
這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。 -
There will be a separate data bus connecting the central processing unit to memory devices.
有一條獨立的數據總線將中央處理機與存儲器連接起來。 -
This high - speed data acquisition card designed is based on pci bus and have high capacity memory interface. it combines high - speed date acquisition and high capacity real - time memory
為此，本文設計了一款基於pci總線且具備可擴展大容量存儲設備介面的高速模擬信號採集卡，將高速數據採集和大容量實時存儲結合在一起。 -
The fourth chapter : in this chapter, it introduces the hardware designing of the dsp system based on pci bus and states every module of the hardware designing : circuit of signal adjusting, filter circuit of anti - overlap, circuit of data - acquisition automatically, expanding circuit of dsp memory, circuit of voltage matching, interfaces circuit of pci etc. it also includes theoretic basis and procedure of pcb designing
第四章介紹基於pci總線的dsp系統硬體設計。敘述了硬體設計的各個模塊：信號調理電路、抗混疊濾波電路、自動數據採集電路、 dsp存儲器擴展電路、電平匹配電路、 pci介面電路等，以及pcb設計的理論基礎和設計過程，並給出了設計和調試的結果。 -
There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。 -
It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc
它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。 -
The work in this thesis was part of a national 05 " project which task was designing the " longtengrl " microprocessor. there are four parts in " longtengrl " microprocessor : integer execution unit ( ieu ), floating point unit ( fpu ), memory subsystem unit ( msu ) and bus interface unit ( biu )
本論文完成存儲子系統單元的設計與實現、 「龍騰r1 」系統的集成、存儲子系統單元的驗證以及在「龍騰r1 」存儲子系統基礎上進行了tracecache的研究，其中重點討論存儲子系統的設計與實現。 -
This software system of chip simulation ' s main function is simulate the main logic circue chips, 8088cpu, memory, registers, data _ bus, address _ bus, control _ bus and other chips. this function is based on the object - oriented technology, construct the chip object by the chip classes that we defined. because this system need to simulate the detail function of computer hardware, so this system simulate the 8088cpu ' s order system, support the basic compile languages. one of the feture of this system is the simulation of a static memory, the room of the memory can be configured by testers from 1k to 64k
由於本系統在模擬過程中需要完全模擬計算機硬體的工作原理，因此本系統還模擬了8088cpu的基本指令系統，支持基本的匯編指令，在實驗過程中可以由實驗者輸入相應的匯編指令以執行操作，並查看各晶元器件的引腳參數變化情況。本系統模擬的一個特點是動態模擬了存儲器的大小，存儲器容量可以由實驗者根據需要自己設置，范圍從1k到64k 。 -
The product has the following characters : all - purpose input, completed separated signal channels, collection of the signal data by scanning, the display technique of lcd big screen, flash memory ; capacious compatible floppy disk, 36 types of signals, multiple alarms, communication of rs232 / 485 and hart confered - link with a view to second generation technique of the field - bus. during the developing course, i used the method of reliability design to design hardware, and researched carefully the process of weak signal. pass to practice, the product has achieved all aim of the design
系統在功能上實現了萬能輸入，信號通道之間的完全隔離，信號的掃描採集，大屏幕lcd顯示技術， flash存儲器進行數據存儲，大容量的具有兼容性的電子軟盤， 36種信號方式，多種報警方式， rs232 / 485通訊，以及著眼于下一代的現場總線技術的hart協議介面等。 -
It has wide frequency width and high frequency relution. the maximum output frequency can get to 80m and the highest frequency relution can get to 1 u hz, the waveform memory is 64k. it has the important reference value for three classical structures - pc bus card, stand alone, vxi module
該任意波形發生器不僅能產生正弦波，方波，三角波等常用的標準信號，還可根據用戶的需要生成任意波形，具有寬頻帶，高的頻率解析度等特點，其波形最高輸出頻率可達80m ，頻率解析度可達1 hz ，波形最大存儲深度為64k ，對于目前三種典型的任意波形發生器的結構? pc總線插卡式，獨立儀器， vxi模塊都有重要的參考價值。 -
The dissertation implements acquisition data high speed transfer with pci bus dma technology and designs four group high speed streaming disk interface to expand high speed and high capacity memory and implement mass storage
本文運用基於pci總線的dma技術實現了採集數據的高速傳輸，並通過設計4組高速流盤介面來外擴高速超大容量存儲器，實現了連續採集的海量存儲。 -
This stage makes heavy use of the video memory and the video memory bus
這個過程中對顯存和顯存總線的負擔比較大。 -
As there are other processor measures such as size of a chip cache, speed of memory bus, and word width, there are at least three other noteworthy measures of beowulf performance
正如其它度量處理器的手段有晶元緩存的大小、內存總線的速度和字寬一樣，至少有三種值得注意的度量beowulf性能的方法。 -
With smp, all memory access is posted to the same shared memory bus
通過smp ，所有的內存訪問都傳遞到相同的共享內存總線。 -
Memory bus bandwidth
內存總線帶寬 -
Numa alleviates these bottlenecks by limiting the number of cpus on any one memory bus and connecting the various nodes by means of a high speed interconnection
Numa通過限制任何一條內存總線上的cpu數量並依靠高速互連來連接各個節點，從而緩解了這些瓶頸狀況。 -
This works fine for a relatively small number of cpus, but not when you have dozens, even hundreds, of cpus competing for access to the shared memory bus
這種方式非常適用於cpu數量相對較少的情況，但不適用於具有幾十個甚至幾百個cpu的情況，因為這些cpu會相互競爭對共享內存總線的訪問。 -
By combining the three lock - unlock pairs into a single lock - unlock pair, performance is improved by reducing instruction count and reducing the amount of synchronization traffic on the memory bus
把三個上鎖-解鎖對組合到一個上鎖-解鎖對，降低了指令數量和內存總線上同步流量的數量，從而提高了性能。
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