memory decoder 中文意思是什麼
memory decoder
解釋
存儲器解碼器-
The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality. cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis. after hdl
本文還設計了與軟體配合能讀、寫閃存的電路以及紅外遙控的硬體解碼電路，經hdl模擬及fpga驗證，所設計的兩種電路能完全滿足晶元商用要求。 -
The main function modules discussed in this paper include : stream media protocols application model and realization, ts parsing module, audio / video decoder, audio / video synchronization model and realization, player memory buffer management module, multi _ task tech under uclinux. we also discuss the difference of the realization of stream media player between two defferent service types : broadcast tv ( btv ) and video - on - demand ( vod )
從功能上，流媒體播放器主要包含幾個大的功能模塊:流媒體協議棧的應用模型及實現機制、多節目復用傳輸流（ ts ）的解析實現、音視頻媒體數據的解碼、音視頻同步機制的設計和實現方法、播放器內存管理模型的設計和實現、 uclinux下多任務的實時調度和高效數據交互技術等。 -
In the part 2 of advanced audio video coding standard avs - p2, many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, symmetric matching, quarter precision interpolation, etc. however, these new features enormously increase the computational complexity and the memory bandwidth requirement, which make motion compensation a difficult component in the implementation of the avs hdtv decoder
在avs - p2中傳統的運動補償技術被進一步改進以獲得更好的編碼性能。這些新的特性包括：預測塊大小可變化1616到88基於矢量三角形的新型mv預測多參考幀最多2幀或4場直接或對稱模式匹配不限制的mv和1 4精度像素插值等。 -
Chapter 3 presents the design and implementation of memory management of rtos for the hdtv integrated source decoder chip
第三章具體描述應用於hdtv信源解碼晶元的實時操作系統存儲管理策略的設計及實現。 -
In this thesis, we research and implement me memory management methods of rtos for the hdtv integrated source decoder chip
本文以hdtv信源集成解碼晶元為開發背景，研究和實現了應用於該soc晶元的實時操作系統的存儲管理策略。 -
High - effective and low - cost memory system the demand for bandwidth and response time of video decoder is analyzed, a high - effective and low - cost multi - entity interlaced ddr sdram controller design and relevant address mapping scheme is proposed
高效低成本的存儲系統設計本文分析了avs和h . 264解碼器對存儲系統帶寬和響應速度的要求，針對ddrsdram延遲長、多bank的特點，設計了一套高效的多體交錯式ddrsdram控制方案和相應的地址映射方式。 -
The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method
這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。 -
The pw328 imageprocessor is a highly integrated solution with an internal adc and a video decoder, with an external memory interface to support more advanced windowing capabilities and high - resolution lcd televisions
Pw328圖像處理晶元是一個高度集成的解決方案，它集成了高速數模轉換、視頻解碼，具有外部存儲介面支持多窗口和高解析度液晶電視能力。 -
Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology
然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
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