peripheral bus 中文意思是什麼

peripheral bus 解釋
外圍總線
  • peripheral : adj. 1. 周圍的，外圍的；外面的；邊緣的。2. 【解剖學】（神經）末梢區域的。vt. -ize 使（某人）處于社會邊緣，使成邊緣人，使受社會排斥。adv. -ly
  • bus : n （pl busses buses）1 公共馬車；公共汽車；客機。2 〈口語〉汽車，機器腳踏車；飛機。3 【電學】信息...
  1. As a new interface caters for rapid development of computer peripheral equipment, universal serial bus ( for short usb ) dispels astriction of communication through traditional serial port and parallel port. it is very suitable for real time image data transmission, which requires high speed. this theme describes two - circuit systems, which utilize usb interface to data from a digital image sensor to pc

    為了迎合計算機上設的快速發展以及消除計算機外設通過串、並口的通訊的局限性，出現了新的計算機外設介面usb （通用串列總線） ，這種新型介面對于實時的視頻傳輸很適用，本文設計了兩套電腦眼基於ez - usb2131q的usb介面系統。
  2. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions

    Vme計算機具有如下性能特點： 1 ，支持多個cpu ， 2 ， 64位的尋址和數據傳輸能力， 3 ， iec 297歐卡標準，機械性能可靠和穩定，並具有可靠的接插件。
  3. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    性能的提高主要是由於三個方面的改進： 1 .處理器及高速緩存性能的優化2 .降低內存瓶頸：通過對powerplus體系結構的改進，使內存性能提高到582mb s memory read bandwidth和640mb s burst write bandwidth 3 .系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mb s ， powerplus ii則能達到80mb s而無須消耗額外的cpu資源。
  4. Peripheral devices in embedded systems are often connected to the mcu as memory - mapped i / o devices, using the microcontroller ' s parallel address and data bus. this results in lots of wiring on the pcb ' s to route the address and data lines, not to mention a number of address decoders and glue logic to connect everything

    由於并行總線擴展時連線過多，外圍器件工作方式各異，外圍器件與數據存儲器混合編址等，都給單片機應用系統設計帶來布線復雜，線路板面積大，易引起emi和esd干擾等困難，這在一些比較復雜的應用系統是難以接受的。
  5. It sends digital signals based on dmx512. pci bus is the data - transporting media between cpu and single - chip computer. at present, there are several kinds of schemes for the pci bus and the peripheral circuit

    （ 2 ）設計以pci總線為cpu和負責處理dmx512仂，議數據的單片機之間數據傳輸媒介的數據通訊卡，研究pci總線的有關特點，比較各種pci介面方案的優缺點，結合實際選出一種切實可行的方案。
  6. At present, the interface mode of many lcm ( lcd module ) products is bus interface mode, which can be divided into serial peripheral interface and parallel peripheral interface

    目前， lcd模組常用的工作方式有總線介面模式，分為串列和并行兩種方式，使用靜態畫面來測試顯示品質。
  7. As a new bus standard in computer peripheral hardware, usb is adopted and widely used in virtual instruments for its ease of use, true plug and play, power supply from bus, high transmission speed, etc. the purpose of this project is to design and develop a virtual instrument that can test and display semiconductor transistor output characteristics curve, instead of tradition instrument which has being used in labs by now

    而usb總線作為一種新興的計算機外設總線標準，由於易用、支持熱插拔、總線供電、傳輸速率高等特點，已經在虛擬儀器當中得到采納與普及。本文介紹了一種實現晶體管特性曲線測量的虛擬測試儀器的設計和製作方案，其可用來取代目前在實驗室中使用的老式的晶體管特性圖示儀。
  8. The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral

    它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。
  9. In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io

    在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。
  10. The clb bus is a kind of on - chip system bus which is usually used to connect ips with high speed and high data width. the peripheral bus that conform the pvci standard usually used to connect ips with low speed and low data width

    Clb總線是一種片上系統總線，一般用來連接高速度、高數據寬度的ip 。而符合pvci標準的外設總線上連接的往往是低速度、低數據寬度的ip 。
  11. 1. study of the clb bus protocol and the pvci protocol ; 2. the design of clb - pvci bridge architecture ; 3. the design of each functional module, include the state machine, the address decoding and peripheral ip selection module, datapath module

    Clb總線協議和pvci協議的研究； 2 clb - pvci橋總體結構的設計； 3各功能模塊的設計，包括狀態機、地址譯碼和外設ip選擇模塊、數據通道模塊； 4
  12. As a kind of the high performance local bus, pci ( peripheral component interconnect ) is extensively used to the extended card of personal computer

    Pci局部總線作為先進的高性能局部總線，被廣泛的用於計算機（ pc ）的擴展卡中。
  13. Pci ( peripheral component interconnect ) bus, which has been the first chosen in recent years for pc local bus because of its high performance, is an excellent bus for multimedia

    Pci （ peripheralcomponentinterconnect ）總線是近年來出現的一個面向多媒體技術的優秀總線，它憑借許多高端性能而成為pc機局部總線的首選。
  14. Pci ( peripheral component interconnect ) local bus is one of the high performance computer system local bus being used broadly today. it ’ s interface has become the very important circuit module of most computer systems

    Pci （ peripheralcomponentinterconnect ）總線是一種高性能，廣泛使用的計算機局部總線，其介面電路已經成為各種計算機系統很重要的功能模塊電路。
  15. From the emergence of pci ( peripheral component interconnect ) in 1993, pci has been widely adopted as a high performance bus protocol and used in various systems ranging from portable computer to supercomputer

    自1993年pci （ peripheralcomponentinterconnect ，外部設備互聯）總線標準建立， pci已經成為一種被廣泛採用的總線結構，應用於從便攜式電腦到大型服務器等多種計算機系統中。
  16. At first, it discusses the way to design a data acquisition and storage system with high speed based on pci ( peripheral component interconnect ) bus, then the author implements the device driver to acquisition the image data with high speed in real time in the kernel mode of system based on researching deeply of the mechanism and structure of kernel mode in windows operating system

    首先討論了pci （ peripheralcomponentinterconnect ? ?外圍部件互連）總線高速多通道數據採集與存儲系統硬體介面設計方法，然後深入討論了基於windows系統核心態結構機制基礎上的設備驅動程序的設計方法，最後討論了cd - 650bx的設計與實現。
  17. The peripheral equipment, which includes serial control, b3g test tools, ddr control, interrupt control, connect the on - chip peripheral bus of powerpc ~ ( tm ) 405. in addition, the clock module and the misc logic module are necessarily to make the b3g test platform work. in order to debug the b3g test platform, the chipscope ~ ( tm ) core is adopted

    在powerpc ~ （ tm ） 405的外圍總線上開發了串口控制器、 b3g測試工具、雙倍數據流（ ddr ）內存控制器、中斷控制器等外設;整個系統還需要時鐘、輔助邏輯等模塊;為了方便b3g測試平臺的調試，將chipscope ~ （ tm ）核也嵌入到了平臺中。
  18. The misc logic module can capture and lock the errors of processor local bus and on - chip peripheral bus. these errors can be shown by light - emitting diode light. the chipscope _ ila core is used for debugging the fpga logic and timing

    而輔助邏輯主要是用來捕獲並鎖定powerpc ~ （ tm ） 405的處理器局部總線（ plb ）和片上外圍總線（ opb ）的錯誤，並通過led燈進行顯示。
  19. Local peripheral bus

    局域邊緣總線
  20. We can connect peripherals to the bus through the box which is on peripheral bus and in so doing we can realize the control and regulation of the bus

    我們將外總線技術引入可穿戴計算機的硬體介面設計，通過總線上的連接器box將外設掛接在總線上。
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